Clock Control Circuit Module Frequency Alignment
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Solution Overview
Problem
Existing signal receivers face challenges in aligning the phase of fast data signals with internal clock signals, leading to decreased sampling accuracy due to large frequency differences between data signals and internal clock signals.
Innovation Solution
A clock control circuit module that includes a clock generation circuit, a sampling circuit, and a control circuit. This module generates a clock signal, samples a first signal to produce first and second sampling signals, and evaluates the frequency shift status between the first signal and the clock signal based on position information from the sampling signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transmission speed of the data signal is increased, then the data transmission efficiency is improved, but the difficulty of aligning the phase of the data signal with the internal clock signal increases
Solution Approach 1:
The patent introduces a frequency detector as an intermediary component between the data signal and the phase detector. This frequency detector first reduces the frequency difference between the data signal and the internal clock signal, creating a preliminary frequency alignment that enables the subsequent phase detector to function effectively. Without this intermediary frequency detection and adjustment stage, the phase detector would be unable to achieve proper phase alignment when the frequency difference is too large.
Solution Approach 2:
The frequency detector performs preliminary frequency alignment before the phase detector attempts phase alignment. By first reducing the frequency difference between the data signal and internal clock signal through frequency detection and adjustment, the system prepares the signals in advance so that the phase detector can then focus on phase alignment without being hindered by large frequency discrepancies.
2Measurement precision
If a frequency detector based on a reference clock signal is used, then the frequency of the internal clock signal can be corrected, but the frequency difference between the data signal and the reference clock signal remains too large for the phase detector to work smoothly
Solution Approach 1:
The patent implements a feedback mechanism where the frequency detector continuously monitors the frequency difference between the data signal and the internal clock signal, and adjusts the internal clock signal frequency accordingly. This closed-loop feedback ensures that the frequency difference is maintained within a range that allows the phase detector to operate reliably, dynamically adapting to frequency variations in the data signal.
Solution Approach 2:
The system dynamically adjusts the internal clock signal frequency based on the frequency detection results. Rather than using a fixed reference clock frequency, the system continuously adapts the clock frequency to match the data signal frequency, ensuring that the frequency difference remains within the operational range of the phase detector under varying transmission conditions.
3Measurement precision
If a frequency detector based on a data signal is used, then the frequency of the data signal can be evaluated, but multiple internal clock signals with different phases are required which are not suitable for all signal receivers
Solution Approach 1:
The patent extracts the frequency detection function from a multi-phase clock signal system and implements it using a single internal clock signal. By removing the requirement for multiple phase-shifted clock signals and achieving frequency detection with a single clock source, the system simplifies the device architecture while maintaining frequency evaluation capability.
Solution Approach 2:
The frequency detector is designed to work with a single internal clock signal that can serve multiple functions: both as the sampling clock and as the reference for frequency detection. This universal approach eliminates the need for separate multi-phase clock signal paths, making the system applicable to all types of signal receivers regardless of their specific clock signal capabilities.
4Device complexity
If no frequency detection mechanism is implemented, then the device complexity is reduced, but the sampling accuracy of the data signal decreases due to large frequency differences
Solution Approach 1:
The patent merges the frequency detection function with the existing clock generation and phase detection circuits. Rather than adding a completely separate frequency detection subsystem, the frequency detector is integrated into the existing signal processing path, sharing common circuit elements and signal paths. This integration approach improves sampling accuracy through frequency alignment while minimizing the increase in overall device complexity.
Data Source
AI summary
A clock control circuit module, a memory storage device, and a clock control method are disclosed. The clock control circuit module is configured to: generate a clock signal; receive a first signal and the clock signal and sample the first signal according to the clock signal to generate a first sampling signal and a second sampling signal; obtain first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal respectively; and evaluate a frequency shift status between the first signal and the clock signal according to the first position information and the second position information.