Clock Control Circuit for Semiconductor Memory Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices experience unnecessary current consumption due to continuous toggling of internal clocks during active mode, even when in a non-operation state, leading to inefficiencies in power management.
Innovation Solution
A clock control circuit that generates a control signal to disable internal clock toggling in non-operation states, comprising a control signal generating unit and a clock transferring unit, utilizing logic operations and signal buffering to synchronize clock enable signals with command signals, thereby preventing external clock transfer and internal clock generation during non-operation states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal clocks are continuously synchronized to external clock in active mode, then clock synchronization is maintained, but unnecessary current consumption occurs during non-operation states
Solution Approach 1:
The clock control circuit dynamically adjusts the transfer of external clock to internal clocks based on operational state. A control signal generating unit monitors command signals (RAS, CAS, WE, BST) and generates a control signal that enables or disables clock transfer accordingly. When in non-operation state during active mode, the control signal prevents external clock from being transferred to delay units, thereby stopping internal clock toggling and reducing current consumption while maintaining the ability to resume synchronization when needed.
2Use of energy by moving object
If internal clocks are disabled to reduce current consumption, then power savings are achieved, but clock synchronization is lost
Solution Approach 1:
The system employs feedback through control signal generation that monitors the state of command signals. The control signal generating unit continuously evaluates whether the memory device is in operation or non-operation state based on command signal status. This feedback mechanism enables the system to automatically enable or disable clock transfer without external intervention, ensuring clock synchronization is maintained when needed while achieving power savings during non-operation states.
3Speed
If clock transfer is continuously enabled, then operational responsiveness is maintained, but energy is wasted during non-operation states
Solution Approach 1:
The clock transfer operation is made periodic rather than continuous. The control signal generating unit periodically evaluates command signals to determine whether clock transfer should be enabled or disabled. This periodic control allows the system to maintain operational responsiveness when commands are active while eliminating energy waste during non-operation states, as clock transfer is suspended only during periods when no commands are being executed.
Data Source
AI summary
A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control signal.