Clock Control Circuit for Register Reset Timing
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Solution Overview
Problem
In digital circuit designs, especially high-speed ones, the inconsistency in reset signal durations across registers leads to incomplete reset within a single clock cycle, causing function errors, frequency reduction, and increased power consumption.
Innovation Solution
A clock control circuit and method that includes a clock adjusting module and clock gating to adjust the clock signal, allowing registers to be reset without requiring a clock cycle, ensuring all registers are reset before receiving a clock signal, thereby avoiding logic errors and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If reset signals are transferred to registers within a single clock cycle, then reset speed is improved, but inconsistent reset durations across registers cause function errors and frequency reduction
Solution Approach 1:
The patent divides the reset process into two independent phases: a reset signal generation phase that does not depend on clock cycles, and a register reset phase that uses clock cycles. The reset signal source generates reset signals asynchronously, and the clock control unit separately manages the clock signal timing, allowing each register to be reset at its optimal moment without forcing all registers to complete reset within a single clock cycle, thus eliminating function errors while maintaining high reset speed
Solution Approach 2:
The patent applies preliminary action by having the reset signal source generate and prepare reset signals before the clock signal reaches the registers. The clock control unit anticipates the register reset timing and adjusts the clock signal accordingly, ensuring that reset operations are initiated in advance and completed before the next clock cycle begins, thereby preventing function errors without reducing overall reset speed
2Loss of time
If timing optimization is used to control reset within one cycle, then reset timing is improved, but standard batteries with high speed and large leakage are selected, leading to increased area and power consumption
Solution Approach 1:
The patent extracts the reset signal generation function from the clock-driven system by introducing a dedicated reset signal source that operates independently of the clock signal. This allows the reset process to be decoupled from clock cycle constraints, eliminating the need to use high-speed batteries with large leakage for timing optimization, thereby reducing power consumption while maintaining precise reset timing through the clock control unit's coordinated management
3Device complexity
If reset signals are sent to all registers simultaneously, then reset operation is simplified, but registers with different reset path lengths cannot be reset completely in one cycle
Solution Approach 1:
The patent applies dynamics by making the clock signal timing adaptive rather than fixed. The clock control unit dynamically adjusts the clock signal timing based on the actual reset completion status of different registers, allowing each register to be reset completely according to its specific path length. This dynamic adjustment ensures consistent reset completion across all registers without increasing operational complexity, as the clock control unit automatically coordinates timing based on feedback from the register reset status
Data Source
AI summary
A clock control circuit includes a clock source, a reset signal source, a register group with a plurality of first registers, and a clock control unit including a clock adjusting module and a clock gating. wherein a first receiving end of the clock adjusting module is connected to the clock source, a second receiving end of the clock adjusting module is connected to the reset signal source; a first receiving end of the clock gating is connected to an output end of the clock adjusting module, a second receiving end of the clock gating is connected to the clock source, an output end of the clock gating is connected to one end of the register group, and the other end of the register bank is connected to the reset signal source. Reset of the register group in the circuit is not limited by one clock period to avoid circuit function errors and power consumption, and have high applicability.