Clock Control Circuit for Side-Channel Power Masking
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Solution Overview
Problem
Existing methods for protecting semiconductor devices from side-channel attacks, such as those described in Patent Document 1, increase power consumption, chip area, and timing design complexity, while offering limited software control over dummy process insertion.
Innovation Solution
The method involves replacing clock oscillation states with pseudo-random numbers to shift processing times, using bitmap circuits and clock control circuits to generate intermittent clocks, thereby masking current consumption patterns and making it difficult to decrypt encryption keys without increasing power consumption or chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock oscillation is randomized to prevent side-channel attacks, then security against power analysis attacks is improved, but timing design complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the clock signal characteristics through controlled jitter insertion and frequency variation. The system dynamically adjusts clock timing parameters using pseudo-random sequences to create unpredictable power consumption patterns, thereby preventing power analysis attacks while maintaining functional correctness through controlled parameter modulation.
Solution Approach 2:
The patent implements periodic action through the use of pseudo-random sequences that periodically modify clock timing. The clock signal undergoes regular intervals of jitter insertion and frequency adjustment, creating a periodic pattern of power consumption variation that effectively masks cryptographic operations from side-channel analysis while maintaining system synchronization.
2Reliability
If dummy processes are inserted via hardware to thwart side-channel attacks, then security is improved, but flexibility in dummy process insertion is reduced
Solution Approach 1:
The patent introduces an intermediary layer between hardware and software through a dedicated control unit that generates pseudo-random sequences. This intermediary component enables software to control dummy process insertion timing and characteristics without direct hardware modification, providing both security effectiveness and software flexibility through the mediating pseudo-random sequence generation mechanism.
Solution Approach 2:
The patent applies dynamics by making the dummy process insertion characteristics variable and adaptable. The system dynamically adjusts the timing, frequency, and pattern of dummy processes based on software-controlled pseudo-random sequences, allowing flexible adaptation to different cryptographic operations and attack scenarios while maintaining hardware-based security protection.
3Reliability
If false current generating circuits are added to mask power consumption, then security against power analysis is improved, but total power consumption and chip area increase
Solution Approach 1:
The patent extracts the false current generation function from a separate dedicated circuit and integrates it into the existing clock control infrastructure. By utilizing the clock control unit and pseudo-random sequence generator already present in the system, the invention eliminates the need for additional false current generating circuits, thereby maintaining security protection while avoiding increases in total power consumption and chip area.
Solution Approach 2:
The patent applies universality by making the clock control unit perform multiple functions: it simultaneously maintains normal clock operation, generates pseudo-random sequences for dummy process insertion, and creates power consumption masking effects. This multi-functional approach eliminates the need for separate dedicated circuits for each function, reducing overall power consumption and chip area while maintaining security effectiveness.
Data Source
AI summary
A semiconductor device provides a method to avoid side-channel attacks. While the logic circuit A for performing the encryption process does not operate, by operating the logic circuit B (performing processing other than the encryption) having a circuit scale of approximately the same as the logic circuit A, the change in the consumption current interlocked with the operation state of the logic circuit A is shielded, it is possible to make it difficult to decrypt the encryption key of the logic circuit A by analyzing the current waveform.