Clock Control Section for Power Reduction in Data Transmission
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Solution Overview
Problem
In high-speed data transmission systems, the need to continuously transfer data to maintain clock synchronization leads to unnecessary power consumption, especially during periods where data transfer is not required.
Innovation Solution
A transmitter and receiver system that embeds a clock signal in data and controls its frequency reduction during predetermined periods, allowing for efficient data transfer while minimizing power consumption by reducing the clock signal frequency only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data transfer is continued constantly to maintain CDR circuit synchronization, then synchronization is maintained, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies periodic action by transferring data only during necessary periods and suspending transfer during unnecessary periods. The CDR circuit is designed to maintain synchronization through periodic data transfer rather than continuous transfer, allowing the system to reduce power consumption while preserving synchronization capability.
Solution Approach 2:
The patent implements dynamics by making the data transfer operation variable - switching between active transfer and suspended transfer states based on necessity. The system dynamically adjusts its operation mode to balance synchronization requirements with power consumption constraints.
2Use of energy by moving object
If clock signal frequency is reduced in predetermined periods, then power consumption is suppressed, but data transfer efficiency may be affected
Solution Approach 1:
The patent applies periodic action by reducing the clock signal frequency during predetermined periods when data transfer is not necessary. This periodic frequency reduction allows the system to suppress power consumption during idle periods while maintaining higher frequency during active data transfer periods to ensure efficiency.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the clock signal frequency based on the necessity of data transfer. The frequency parameter is changed from high to low during predetermined periods, enabling power suppression without permanently compromising transfer efficiency.
Data Source
AI summary
The present disclosure relates to a transmitter and a transmission method and a receiver and a reception method that make it possible to suppress an increase in power consumption. Data in which a clock signal is embedded is transmitted, and a frequency of the clock signal embedded in the data is controlled to reduce the frequency of the clock signal in a predetermined period. Alternatively, data in which a clock signal is embedded and a notification indicating that a frequency of the clock signal is variable are received, and a frequency of the received data is reduced in a predetermined period, on the basis of the received notification. The present disclosure is applicable to, for example, a transmitter, a receiver, a signal processor, a controller, an information transfer system, a transmission method, a reception method, a program, or the like.