Clock Control Circuit for Non-Overlapping Strobe Alignment
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in processing two data within a short clock period due to overlapping pulse widths of rising and falling strobe signals, leading to inaccurate data alignment and defective operations.
Innovation Solution
A clock control circuit that adjusts the pulse widths of rising and falling strobe signals to prevent overlap, ensuring non-overlapping enable pulse widths for accurate data alignment and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pulse widths of rising and falling strobe signals are extended to improve data sampling accuracy, then the data alignment precision is improved, but the overlap between rising and falling strobe signals occurs causing defective operations
Solution Approach 1:
The patent applies dynamics by making the strobe signal pulse widths adjustable rather than fixed. The clock control circuit dynamically adjusts the pulse widths of rising and falling strobe signals based on operating conditions to prevent overlap while maintaining adequate sampling margins. This dynamic adjustment resolves the contradiction by allowing the system to optimize for precision when needed while avoiding defective operations under different conditions.
Solution Approach 2:
The patent changes the temporal parameters (pulse widths) of the strobe signals through the clock control circuit. By modifying the duration of rising and falling strobe signals, the system can prevent overlap between them while maintaining sufficient sampling time. This parameter adjustment directly addresses the contradiction between achieving precise data alignment and preventing defective operations.
2Productivity
If the clock period is reduced to increase operating speed, then the productivity is improved, but the time available to process two consecutive data is insufficient leading to processing errors
Solution Approach 1:
The patent segments the data processing into two separate paths: external data transfer synchronized with both rising and falling edges, and internal core processing synchronized with a single rising edge. This segmentation allows the device to operate at high speeds externally while maintaining adequate processing time internally, resolving the contradiction between speed and accuracy.
Solution Approach 2:
The patent uses periodic action by employing a main clock that runs at a lower frequency (half the I/O clock frequency) for internal core operations. This periodic synchronization ensures that internal processing has sufficient time to complete while the external interface operates at higher speeds, thus resolving the speed-accuracy tradeoff.
3Reliability
If the pulse widths of rising and falling strobe signals are increased to improve data latching reliability, then the latching reliability is improved, but the overlap between adjacent strobe signals occurs causing data misalignment
Solution Approach 1:
The clock control circuit dynamically adjusts strobe signal characteristics based on timing requirements. When latching reliability is the priority, it extends pulse widths appropriately, but when alignment precision is critical, it reduces overlap by adjusting the timing and duration of rising versus falling strobe signals. This dynamic control resolves the contradiction between reliability and precision.
Data Source
AI summary
A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.