Clock Controller Frequency Switching for DFS Delay Mitigation
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Solution Overview
Problem
In semiconductor integrated circuits that dynamically control clock frequency, performance deterioration occurs due to delays in DFS control signals, leading to inefficient power consumption and operational delays during busy periods.
Innovation Solution
The semiconductor integrated circuit statistically predicts the duration of low-frequency operation and proactively returns to high frequency before predicted delays occur, using a clock controller with a PLL circuit, frequency dividers, and clock gating circuits to manage clock frequency based on activity monitoring and statistical processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock frequency is dynamically controlled to reduce power consumption during non-busy periods, then power consumption is reduced, but performance deterioration occurs due to delays in DFS control signals during busy periods
Solution Approach 1:
The patent applies preliminary action by statistically predicting the duration of non-busy periods in advance and proactively returning the clock frequency to high frequency before the predicted delay period expires. The controller predicts how long the non-busy state will continue and switches back to high frequency prior to when performance deterioration would occur, thus preventing the harmful effect before it happens.
Solution Approach 2:
The patent implements feedback by monitoring the actual busy/non-busy periods and comparing them with predicted values. The controller statistically processes the relationship between DFS control signal transitions and actual busy period durations, using this feedback to refine predictions and improve the timing of frequency transitions, thereby optimizing both power consumption and performance.
2Loss of energy
If the clock frequency is lowered during non-busy periods, then power consumption is reduced, but operational delays occur when transitioning back to high frequency
Solution Approach 1:
The patent applies preliminary action by predicting the duration of non-busy periods in advance and proactively switching back to high frequency before the predicted delay period expires. The controller statistically determines the relationship between DFS control signal transitions and actual busy period durations, then uses this prediction to timing frequency transitions optimally, thus preventing operational delays before they occur.
3Productivity
If statistical prediction is used to determine when to return to high frequency, then performance is maintained, but device complexity increases due to additional prediction and control circuitry
Solution Approach 1:
The patent applies universality by designing the clock controller to perform multiple functions: it not only controls frequency transitions but also statistically predicts busy period durations and determines optimal switch-back timing. This multi-functional approach consolidates prediction and control capabilities into a single controller unit, reducing overall system complexity despite the added predictive functionality.
Data Source
AI summary
A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.