Clock Controller Queue Delay Asymmetry Compensation

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Solution Overview

Problem

Conventional clock synchronization protocols in packet-data networks face challenges in compensating for dynamic asymmetry caused by queue-induced delays, which can lead to inaccuracies in time synchronization between master and slave clocks, especially under heavy network loads and in end-to-end secured communication paths.

Innovation Solution

A clock management method and a clock controller that periodically collect data on queue sizes and link rates from transit nodes to estimate and compensate for queue-induced delay asymmetry, providing correction parameters to slave clocks to improve synchronization accuracy without relying on 'lucky' packets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional clock synchronization protocols are used in packet-data networks, then basic time synchronization is achieved, but synchronization accuracy deteriorates under heavy network loads due to queue-induced delays

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidsynchronization reliability under heavy load
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The system performs preliminary measurement of queue sizes and link rates at transit nodes before timing packets traverse the network path. This advance collection of network state data enables the calculation of expected queue-induced delays, which are then used to pre-compensate the measured delay values, thereby maintaining synchronization accuracy even under heavy network loads

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where synchronization performance is continuously monitored and compared against expected values derived from queue size and link rate measurements. When deviations are detected, the system adjusts its delay compensation calculations accordingly, creating a closed-loop control system that maintains synchronization accuracy despite varying network conditions

Inventive Principle:
Principle #23Feedback

2Measurement precision

If static asymmetry compensation is used, then compensation for fixed delay differences is achieved, but dynamic queue-induced delay asymmetry cannot be compensated

Engineering Contradiction:
Improvedelay compensation accuracyVSAvoidadaptability to dynamic network conditions
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The system transitions from static asymmetry compensation to dynamic compensation by continuously measuring queue sizes and link rates at transit nodes. These time-varying measurements enable the system to calculate and apply dynamic delay compensation values that adapt to changing network conditions, thereby compensating for both static and dynamic components of delay asymmetry

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the compensation parameters from fixed static values to dynamic values derived from real-time queue size and link rate measurements. By adjusting the delay compensation parameter based on measured network state, the system achieves accurate compensation for dynamic queue-induced delays while maintaining compatibility with existing synchronization protocols

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If 'lucky' packets are relied upon for asymmetry measurement, then delay asymmetry can be estimated, but accuracy is lost when network nodes are heavily loaded and lucky packets are unavailable

Engineering Contradiction:
Improvedelay asymmetry measurement accuracyVSAvoidmeasurement reliability under heavy load
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The system extracts delay asymmetry information from the measured queue sizes and link rates at transit nodes, rather than relying on the arrival of specially timed 'lucky' packets. This extraction approach separates the measurement process from packet timing luck, enabling continuous and reliable asymmetry measurement regardless of network load conditions

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system enables transit nodes to self-report their queue sizes and link rates, providing the necessary data for delay asymmetry calculation without requiring special measurement packets. This self-service approach ensures that measurement data is continuously available from all transit nodes, eliminating the unreliability associated with lucky packet availability under heavy load

Inventive Principle:
Principle #25Self-service

4Reliability

If end-to-end secured communication paths are used, then security is improved, but queue-induced delay asymmetry compensation becomes more difficult

Engineering Contradiction:
Improvecommunication securityVSAvoidcompensation system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system introduces an intermediary component that collects queue size and link rate measurements from transit nodes and provides delay compensation data to the synchronization protocol. This intermediary layer handles the complexity of measuring and compensating for queue-induced delays, allowing the secured communication path to maintain both security and synchronization accuracy without requiring complex modifications to the encryption/decryption process

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3382918B1System and method of clock management in a packet data network
Publication Date: 2022.09.28 ADVA OPTICAL NETWORKING SP ZOO
  • EP3382918B1 patent drawingFigure 1
  • EP3382918B1 patent drawingFigure 2
  • EP3382918B1 patent drawingFigure 3

AI summary

There is provided a method of clock management in a packet data network (PDN) implementing a time-transfer protocol and a clock controller configured to operate therein. The clock controller is configured to: obtain topology data informative of a master clock node and a slave clock node constituting end points of a PTP path in the PDN and further informative of at least part of transit nodes of said PTP path; periodically obtain data informative of queue size and link rate characterizing, during a collection period, the at least part of transit nodes in master-slave (MS) and slave-master (SM) directions; for each collection period, use the obtained queue-related data to estimate queue-induced delay asymmetry of the PTP path; and send the estimated value of queue-induced delay asymmetry to the slave node, the estimated value to be used by a clock residing on the slave node as delay asymmetry correction parameter.