Clock Signal Conversion Circuit With Duty-Cycle Distortion Feedback
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Solution Overview
Problem
Half-clock rate transmitter circuits for high-speed communication links suffer from duty-cycle distortion (DCD) due to mismatches in PMOS and NMOS devices, leading to reduced output eye diagram width, decreased timing margin, and lower data transmission speeds, with conventional DCD correction solutions being inaccurate and power-consuming, especially for sub rail-to-rail logic and long-distance transmission.
Innovation Solution
A clock signal conversion circuit with an amplification stage that converts sub rail-to-rail differential clock signals to full rail-to-rail signals and a duty cycle distortion correction circuit using a low-pass filter and transconductance amplifier to provide feedback and correct duty cycle differences, along with a common-mode loop to ensure equal average duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DCD correction solutions are used, then duty cycle distortion is corrected, but power consumption increases significantly
Solution Approach 1:
The patent changes the operating parameters by using a divide-by-2 block operating at half the frequency of the original clock signal. This parameter change reduces power consumption since dynamic power is proportional to frequency, while still achieving DCD correction through the feedback mechanism that operates at the lower frequency.
Solution Approach 2:
The patent employs periodic action by using a divide-by-2 block that generates a clock signal at half the original frequency. This periodic operation at reduced frequency allows the feedback mechanism to correct DCD with lower power consumption compared to continuous high-frequency operation.
2Length of moving object
If the clock signal is transmitted over long routing distances, then signal distribution is achieved, but duty cycle distortion and attenuation increase
Solution Approach 1:
The patent implements a feedback mechanism where the divided clock signal is fed back through a buffer and combined with the original clock signal. This feedback loop compensates for duty cycle distortion that occurs during long-distance transmission, maintaining signal integrity despite routing challenges.
Solution Approach 2:
The patent introduces an intermediary divide-by-2 block and buffer stage between the clock source and the final output. This intermediary circuitry acts as a mediator that corrects duty cycle distortion caused by long routing distances, ensuring accurate clock signal delivery.
3Measurement precision
If higher-bit DAC is used to increase calibration accuracy, then measurement precision improves, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces the complex higher-bit DAC solution with a simpler divide-by-2 block and feedback mechanism. This alternative approach achieves the necessary calibration accuracy without requiring complex high-resolution digital-to-analog conversion circuitry, thereby reducing both device complexity and power consumption.
Data Source
AI summary
A clock signal conversion circuit includes an amplification circuit configured to amplify a differential clock signal having sub rail-to-rail voltage swings relative to a supply voltage, such that an amplified differential clock signal output by the amplification circuit has complementary positive and negative signal components with full rail-to-rail voltage swings relative to the supply voltage. A duty cycle distortion correction circuit includes: a filter having a cutoff frequency below the frequency of the differential clock signal and configured to output a differential voltage that is proportional to a difference in duty cycle between the positive and negative signal components of the amplified differential clock signal; and a transconductance amplifier configured to convert the differential voltage to a differential current that is provided to the amplification circuit as feedback for reducing the duty cycle difference between the positive and negative signal components of the amplified differential clock signal.