Clock Converter for FPGA Sensor Integration
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Solution Overview
Problem
The limited number of PLL and dedicated clock pins in FPGAs restricts the connection of multiple sensors with dual clock signals, such as cameras, limiting their integration with data processing devices like image sensors.
Innovation Solution
A data processing device and aerial vehicle configuration that includes a sensor, a clock converter, and a processor, where the clock converter converts differential clock signals from multiple sensors into a single-ended clock signal, allowing a single FPGA to process data from multiple sensors without increasing size, weight, or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual clock signals are directly connected to FPGA clock pins, then clock synchronization is achieved, but the number of connectable sensors is limited due to limited PLL and clock pin resources
Solution Approach 1:
The patent introduces a clock converter as an intermediary device between the sensor and FPGA. The clock converter receives dual differential clock signals from the sensor, converts them into a single-ended clock signal, and outputs it to the FPGA. This mediator resolves the conflict by transforming the clock signal format to match FPGA requirements while enabling sensor connection without consuming additional FPGA clock pins or PLL resources.
2Productivity
If multiple sensors with dual clock signals are connected to a single FPGA, then data processing capability is improved, but the limited PLL and clock pin resources become a bottleneck
Solution Approach 1:
The patent changes the parameter of clock signal configuration from dual differential signals to a single single-ended signal through the clock converter. This parameter transformation allows multiple sensors to share a single FPGA clock pin, effectively increasing the quantity of connectable sensors without requiring additional FPGA clock pin resources, thereby improving overall data processing capability.
3Speed
If LVDS links are used for high-speed data transmission, then data transmission rate is improved, but each LVDS link occupies one PLL and one pair of dedicated clock pins
Solution Approach 1:
The clock converter serves as an intermediary that decouples the LVDS data link from the clock pin resource requirement. By converting the dual differential clock signals to a single single-ended clock signal externally, the FPGA only needs one clock pin regardless of how many LVDS links are used, thus maintaining high-speed data transmission while reducing PLL and clock pin occupation.
Data Source
AI summary
A data processing device and an aerial vehicle are provided. The device comprises a sensor, a processor, and a clock converter. A data signal output pin of the sensor is connected with a data signal input pin of the processor. The sensor comprises at least two clock output pins, each of which is connected with one of two input pins of the clock convert. An output pin of the clock converter is connected with a clock input pin of the processor. The dock converter is configured to convert clock signals input from various input pins into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.