Output Clock Correction Circuit Using FIFO-Guided Time Stamp Adjustment
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Solution Overview
Problem
Accurate output clock recovery in serial data communications is challenging due to frequency disparities between source and output clocks, leading to jitter-related transmission errors and FIFO buffer overflow/underflow issues, compromising frame recovery and picture stability.
Innovation Solution
A circuit with an output clock feedback loop, FIFO buffer, and time stamp adjuster is used to adjust the output clock phase and frequency based on time stamp components and FIFO buffer status, preventing overflow/underflow by selectively adjusting the time stamp component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL is used for output clock recovery, then clock synchronization is improved, but jitter increases causing transmission errors
Solution Approach 1:
The patent implements a feedback mechanism by monitoring FIFO buffer data levels and using this information to adjust the time stamp component M. The buffer monitor continuously tracks the actual data level and compares it against target thresholds, creating a closed-loop system that dynamically corrects clock frequency deviations without the jitter accumulation problems of conventional PLLs.
Solution Approach 2:
The patent changes the time stamp parameter M dynamically based on FIFO buffer status. When the buffer data level deviates from the target range, the system adjusts M by a calculated percentage to correct the output clock frequency. This parameter adjustment approach avoids the deterministic jitter inherent in traditional PLL frequency synthesis methods.
2Speed
If conventional PLL frequency adjustment is used, then output clock frequency control is improved, but FIFO buffer overflow/underflow occurs
Solution Approach 1:
The system uses the FIFO buffer data level as direct feedback to control frequency adjustment. The buffer monitor detects when data levels approach overflow or underflow thresholds and triggers time stamp adjustments accordingly. This feedback-driven approach ensures frequency control is tightly coupled to actual buffer status, preventing overflow and underflow conditions.
Solution Approach 2:
The system performs self-correction by automatically adjusting the time stamp component M based on its own FIFO buffer status without requiring external intervention. The time stamp adjuster uses the offset calculation between actual and desired data levels to determine the appropriate frequency correction, enabling the system to self-regulate and maintain stable operation.
3Measurement precision
If time stamp component is adjusted frequently, then FIFO buffer level control is improved, but clock stability deteriorates
Solution Approach 1:
The patent applies partial adjustment by only modifying the time stamp component M when the FIFO buffer data level actually deviates from the target range. The buffer monitor compares the actual level against upper and lower thresholds, and adjustments are made only when necessary. This selective adjustment approach maintains clock stability while achieving precise buffer level control, avoiding unnecessary frequency changes that would disrupt clock stability.
Data Source
AI summary
An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.