Clock Correction Circuit Using Lower-Bit Error Extraction
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Solution Overview
Problem
Existing clock correction circuits for power meters, such as those described in Japanese Unexamined Patent Application Publication No. 2000-315121, face challenges in achieving desired accuracy for frequency corrections at arbitrary times, leading to prolonged testing times and inability to use the correction clock as a recovery pulse due to accumulated frequency errors.
Innovation Solution
A clock correction circuit that accumulates frequency errors and changes the operation clock state when a predefined bit changes, extracting lower-bit values to generate a correction clock using a second clock with a higher frequency, ensuring accurate frequency correction at arbitrary times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a correction clock is generated by accumulating frequency errors until a certain value is reached, then the correction can be performed with a simple configuration, but the correction clock includes frequency errors during the accumulation period and cannot satisfy desired accuracy when detected at arbitrary times
Solution Approach 1:
The patent segments the accumulated value into multiple bits, where a predefined bit (MSB) triggers correction and lower bits provide fine-tuned frequency adjustment. This segmentation allows the correction clock to achieve high accuracy at arbitrary times while maintaining a relatively simple circuit configuration.
Solution Approach 2:
The patent performs preliminary accumulation of frequency errors in a register before generating the correction clock. By pre-calculating and storing the accumulated value, the system can immediately generate an accurate correction clock when needed, without requiring long testing periods to verify accuracy.
2Productivity
If the accumulated value of frequency errors is corrected only when it reaches a certain value, then the correction is performed in batches, but this leads to prolonged testing time to verify accuracy
Solution Approach 1:
By segmenting the accumulated value into bits, the patent enables verification of correction accuracy at any point in time rather than waiting for batch completion. The lower bits provide continuous frequency adjustment information that can be checked immediately, significantly reducing testing time.
Solution Approach 2:
The patent replaces the mechanical waiting process (accumulating until a threshold is reached) with a digital bit-extraction method. Instead of physically waiting for the accumulated value to reach a certain level, the system extracts the required precision from the lower bits of the accumulated value, enabling immediate verification and reducing testing time.
3Adaptability or versatility
If the correction clock is generated with accumulated frequency errors, then it cannot be used as a recovery pulse, but extracting lower-bit values enables accurate correction and versatile usage
Solution Approach 1:
The patent extracts the lower-bit values from the accumulated frequency error value to generate the correction clock. This extraction process removes the accumulated error component while retaining the precise frequency adjustment information, enabling the correction clock to be used as a recovery pulse and for other time-critical applications.
Solution Approach 2:
The patent changes the parameter used for correction from the entire accumulated value to specifically the lower-bit values of the accumulated value. This parameter change transforms the correction clock from an inaccurate signal with accumulated errors into a precise signal suitable for recovery pulses and other versatile applications.
Data Source
AI summary
An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.