Clock Correction Circuit Using SOF Feedback and Fractional-N PLL
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Solution Overview
Problem
Current clock generation and correction circuits in data communication systems face challenges in achieving high accuracy without using external oscillator components, which are costly and consume additional chip area, and require additional circuitry for generating accurate clock signals at various frequencies.
Innovation Solution
A clock generation and correction (CGC) circuit comprising a clock and data recovery (CDR) circuit, start-of-frame (SOF) detector circuit, counter, digital logic circuit, and fractional-N Phase Lock Loop (PLL) that adjusts the local clock signal frequency based on embedded data signal patterns and time markers to enhance accuracy and adapt to different frequencies without external timing components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an on-chip RC oscillator is used to generate the local clock signal, then the device cost is reduced and chip area is saved, but the frequency stability and accuracy of the clock signal deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the received data signal containing time markers is used to detect and correct the frequency accuracy of the locally generated clock signal. The CDR circuit and SOF detector continuously monitor the clock accuracy based on embedded data patterns and generate correction signals to adjust the oscillator frequency, thereby maintaining ±2500 PPM accuracy without external components.
Solution Approach 2:
The system uses the received data signal itself as the reference for clock correction. By extracting time markers from the incoming data stream and comparing them with locally generated timing, the system performs self-diagnosis and self-correction of clock accuracy, eliminating the need for external oscillator components while maintaining high precision.
2Measurement precision
If an external crystal oscillator is used to generate the local clock signal, then the frequency stability and accuracy of the clock signal are improved, but the device cost increases and additional chip area is consumed
Solution Approach 1:
The patent extracts the timing reference information from the received data signal itself by detecting start-of-frame (SOF) markers and other embedded time indicators. This extracted timing information replaces the function of external crystal oscillators, allowing the system to achieve high clock accuracy using only on-chip components and eliminating the need for expensive external oscillator components.
Solution Approach 2:
The received data signal serves multiple functions: it carries both the actual data information and embedded timing reference markers. The system simultaneously uses the data signal for both data reception and clock synchronization, making the data signal a multi-functional element that eliminates the need for separate external timing components.
3Stability of the object's composition
If an external crystal oscillator is used to generate the local clock signal, then the frequency stability is improved, but additional circuitry is required for obtaining accurate clock signals at various frequencies
Solution Approach 1:
The patent implements a dynamic frequency adjustment mechanism where the oscillator frequency is continuously可调 based on the detected timing errors from received data signals. The system can adapt to different frequencies and maintain stability by dynamically correcting the clock signal, eliminating the need for multiple fixed-frequency external oscillators or complex frequency synthesis circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CGC circuit achieves accurate local clock signal generation with an accuracy of ±2,500 parts per million or higher, correcting the frequency as needed, thereby enhancing data transmission accuracy without the need for external oscillators, reducing costs, and optimizing chip area.
Implementation Method 1
a fractional-N Phase Lock Loop (PLL) circuit that modifies the intermediate clock signal based on the frequency adjustment signal
Data Source
AI summary
A clock generation and correction (CGC) circuit comprises a clock and data recovery (CDR) circuit, a start-of-frame (SOF) detector circuit, a counter, a digital logic circuit, a fractional-N phase locked loop (PLL), and an oscillator circuit. The CDR receives an input data signal and an internal clock signal and generates a recovered data signal. The SOF detector circuit generates a toggle signal based on a comparison of the recovered data signal to a predetermined data signal pattern. The counter generates a clock cycle count signal based on the toggle signal. The digital logic circuit generates a frequency adjustment signal based on an error in the frequency of the clock signal. The oscillator circuit generates an intermediate clock signal. The fractional-N PLL circuit receives the frequency adjustment signal and the intermediate clock signal and modifies the internal clock signal based on the frequency adjustment signal.