Shared Buffer Clock Domain Crossing With Channel Indicators
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Solution Overview
Problem
The overhead associated with transmitting data within data processors increases as processor size grows, particularly when crossing clock domains, and existing techniques for reducing this overhead are complicated by the need to manage multiple clock domains.
Innovation Solution
A buffer circuitry with multiple data entries and indicator storage is used to store and manage data blocks across clock domains, allowing independent clock signals and enabling data transmission between clock domains by associating data blocks with their respective channels using indicator entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate buffers are provided for each data channel across clock domains, then data transmission reliability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent merges multiple separate buffers into a single shared buffer that handles data from multiple data channels. Instead of providing dedicated buffers for each channel across the clock domain boundary, the invention uses one buffer with multiple entries that can store data from different channels, thereby reducing the number of buffers while maintaining reliable data transmission through proper channel identification and selection mechanisms.
Solution Approach 2:
The patent introduces an intermediary mechanism using indicator entries associated with each buffer entry. These indicators act as mediators that track which data channel each buffer entry belongs to, enabling the selection circuitry to correctly identify and retrieve data from the appropriate channel without needing separate buffers for each channel.
2Device complexity
If shared buffers are used for multiple data channels, then device complexity is reduced, but data association and ordering accuracy deteriorates
Solution Approach 1:
The patent uses indicator entries as intermediary structures that are stored alongside data entries in the buffer. Each indicator entry is associated with a specific data channel and provides identification information about the data block stored in the corresponding buffer entry. This intermediary mechanism enables accurate tracking of data channel associations within the shared buffer.
Solution Approach 2:
The patent creates a copy of the data channel identification information by storing indicator entries that replicate the channel association metadata alongside the actual data blocks in the buffer. This copying of identification information allows the selection circuitry to accurately determine which data channel each buffer entry corresponds to, maintaining data association accuracy without requiring separate physical buffers.
3Quantity of substance
If multiple data channels share the same buffer, then overhead is reduced, but data ordering and read/write rate coordination becomes complicated
Solution Approach 1:
The patent implements dynamic data management capabilities where the selection circuitry can flexibly choose which buffer entry to access based on real-time needs. The system dynamically tracks which data channels have data available and which entries should be selected for consumption, allowing coordinated read/write operations across multiple channels without requiring complex fixed structures for each channel.
Solution Approach 2:
The patent employs feedback mechanisms where the selection circuitry references the indicator entries to determine the associated data channel for candidate buffer entries. This feedback loop enables the system to make informed decisions about which data to retrieve next, coordinating read operations across multiple data channels with varying read and write rates while maintaining proper ordering and reducing overhead.
Data Source
AI summary
An apparatus comprises buffer circuitry having a plurality of data entries each arranged to store a data block, where each data block has an associated data channel. The buffer circuitry is configured to receive data blocks from producer circuitry controlled by a first clock signal and to provide the data blocks to consumer circuitry controlled by a second clock signal. The apparatus also provides indicator storage having a plurality of indicator entries, wherein each data entry has an associated indicator entry and, for a given data entry storing a given data block, the associated indicator entry is configured to indicate the associated data channel for the given data block. Selection circuitry is provided to select a data entry from which to provide a data block to the consumer circuitry, by referencing the plurality of indicator entries.