Deterministic Clock Crossing With PLL-Synced FIFO Reset
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-bandwidth interconnections between chips require significant power and chip area, making them undesirable for applications needing reduced power consumption and smaller chip sizes.
Innovation Solution
The implementation of on-package input/output (OPIO) interfaces with impedance-matched CMOS transmitters and receivers, minimal electrostatic discharge protection, and deterministic forwarded clock signals to achieve high bandwidth at low power and latency, using length-matched routing and phase-locked loop (PLL) synchronization for clock alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections, then data transfer bandwidth is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent replaces conventional electrical I/O interfaces with a hybrid optical-electrical interface. Optical signals are used for high-bandwidth data transfer between chips, while electrical signals handle control and clock functions. This substitution reduces power consumption and chip area requirements compared to purely electrical high-bandwidth interfaces
Solution Approach 2:
The patent implements a multi-functional interface where a single physical connection handles both optical data transmission and electrical clock signal distribution. The optical interface carries data signals while electrical traces provide clock synchronization, combining multiple functions into one integrated solution that reduces overall system complexity and resource requirements
2Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections, then data transfer bandwidth is improved, but chip area increases significantly
Solution Approach 1:
The patent replaces conventional electrical I/O interfaces with a hybrid optical-electrical interface. Optical signals are used for high-bandwidth data transfer between chips, while electrical signals handle control and clock functions. This substitution reduces power consumption and chip area requirements compared to purely electrical high-bandwidth interfaces
Solution Approach 2:
The patent transitions from purely two-dimensional electrical signal routing to a three-dimensional hybrid approach by incorporating optical fibers that can be routed through different layers and dimensions of the chip package. This allows for more efficient space utilization and reduced chip area footprint
3Reliability
If asynchronous buffer reset is used to handle clock skew, then clock domain crossing reliability is improved, but buffer size and latency increase
Solution Approach 1:
The patent applies preliminary action by pre-aligning clock phases using phase-locked loops (PLLs) before data transfer begins. Deterministic delay elements are pre-configured to compensate for known skew amounts, allowing synchronous buffer reset instead of requiring large asynchronous buffers. This preliminary synchronization reduces the buffer size needed and minimizes latency while maintaining reliability
4Measurement precision
If deterministic forwarded clock is used with PLL synchronization, then clock alignment precision is improved, but system complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-aligning clock phases using phase-locked loops (PLLs) before data transfer begins. Deterministic delay elements are pre-configured to compensate for known skew amounts, allowing synchronous buffer reset instead of requiring large asynchronous buffers. This preliminary synchronization reduces the buffer size needed and minimizes latency while maintaining reliability
Data Source
AI summary
Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock.