Clock Crossing Interface for IC Generation
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Solution Overview
Problem
Integrated circuit design and testing face challenges with clock domain crossings, particularly in transferring digital signals between different clock domains, which can lead to issues like metastability, data loss, and incoherency.
Innovation Solution
A system and method for automatically generating clock crossings between modules in different clock domains, determining signaling protocols, directionality, and clock crossing types based on module data, using logic such as multi-flop synchronizers, MUX recirculation, or FIFO buffers to facilitate reliable signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual design and verification of clock crossings is performed, then reliability can be ensured, but development time and complexity increase significantly
Solution Approach 1:
The system automatically generates clock crossing logic based on module interfaces and clock domain information, allowing the design tool to serve itself without requiring manual intervention from engineers for each clock crossing implementation
Solution Approach 2:
The system changes parameters such as synchronizer depth, FIFO depth, and clock crossing type based on automatically analyzed clock frequencies and data requirements, transforming manual parameter selection into an automated process
2Reliability
If manual selection of clock crossing types is performed, then optimal solution can be chosen, but device complexity and engineering effort increase
Solution Approach 1:
The system analyzes clock frequency ratios and data requirements to automatically determine the optimal clock crossing type (synchronous, asynchronous, FIFO), providing feedback-driven selection rather than manual guesswork
Solution Approach 2:
The automated system handles multiple clock crossing scenarios (synchronous, asynchronous, FIFO-based) through a single unified approach, making the design process universal rather than requiring separate procedures for each case
3Reliability
If comprehensive clock domain analysis is performed, then signal transfer reliability is improved, but manufacturing and verification time increase
Solution Approach 1:
The system performs clock domain analysis and clock crossing generation as preliminary automated steps during the design process, completing complex analysis before implementation rather than during verification
Solution Approach 2:
The system replaces manual mechanical analysis processes with automated computational algorithms that quickly determine clock domain relationships and generate appropriate crossing logic without human intervention
Data Source
AI summary
Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.