Clock Generator Duty Cycle Control with Current-Mode Capacitor Feedback
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Solution Overview
Problem
Existing clock generation circuitries face challenges in achieving precise 50% duty cycle control, especially in high-performance applications requiring wide dynamic ranges and frequency variations, due to sensitivity to power supply variations and complexity in maintaining accuracy across different operating conditions.
Innovation Solution
A clock generator circuit utilizing a D-type flip-flop and current mode processing with a single capacitor and comparator, where P-type and N-type transistors form a duty cycle detection circuit with equal current sources, and a comparator adjusts the duty cycle by controlling the charging and discharging of a capacitor, allowing for precise duty cycle control with reduced sensitivity to power supply variations and increased bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital delay line approach is used for duty cycle control, then the duty cycle can be controlled over a wide dynamic range, but the circuit complexity increases and sensitivity to power supply variations worsens
Solution Approach 1:
The patent extracts the duty cycle control function from complex digital delay line circuits and implements it using a simplified analog approach with a single capacitor and comparator. The core timing function is isolated to essential components only, removing unnecessary digital logic while maintaining wide duty cycle adjustment capability through analog control voltage.
Solution Approach 2:
The patent replaces the digital delay line mechanism with an analog capacitor charging/discharging system. Instead of using digital logic gates and programmable delay elements, the invention uses continuous analog voltage control of capacitor charge time to achieve duty cycle adjustment, fundamentally substituting the control mechanism to reduce complexity.
2Reliability
If traditional duty cycle control circuits are used, then they can provide basic functionality, but they exhibit high sensitivity to power supply noise and variations
Solution Approach 1:
The patent introduces a capacitor as an intermediary energy storage element between the power supply and the timing function. This capacitor acts as a buffer that decouples the timing circuit from power supply variations, absorbing noise and providing stable timing references regardless of power supply fluctuations.
Solution Approach 2:
The patent creates equipotential conditions by using the capacitor to maintain stable voltage levels during charging and discharging cycles. The comparator detects voltage thresholds that remain constant despite power supply variations, ensuring that duty cycle timing points are established at consistent potential levels independent of supply noise.
3Measurement precision
If complex duty cycle control circuits are implemented, then precise duty cycle can be achieved, but the bandwidth and frequency operation capability are limited
Solution Approach 1:
The patent segments the duty cycle control into two independent functions: a fast comparator for precise threshold detection and a simple RC charging circuit for timing. This segmentation allows the comparator to operate at high speeds for accurate edge detection while the capacitor provides the timing function, enabling both precision and high bandwidth operation.
Solution Approach 2:
The patent substitutes complex digital timing logic with simple analog RC charging dynamics. The capacitor charging time constant naturally provides precise timing without requiring complex logic circuits, and this analog mechanism can operate at much higher frequencies than digital implementations due to its continuous and instantaneous response characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise duty cycle control over a wide dynamic range with reduced complexity and increased bandwidth, allowing for higher frequency operation while being less sensitive to power supply noise and variations, effectively addressing the limitations of previous designs.
Implementation Method 1
a comparator adjusts the duty cycle by controlling the charging and discharging of a capacitor
Implementation Method 2
a single capacitor and comparator, where P-type and N-type transistors form a duty cycle detection circuit with equal current sources, and a comparator adjusts the duty cycle by controlling the charging and discharging of a capacitor
Data Source
AI summary
A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.