Clock Cycle Error Detection Using Delayed Signal Comparison
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Solution Overview
Problem
Conventional clock error detection circuits become complex due to the need for a high-speed clock signal and a counter to measure its pulses, making it difficult to achieve high detection accuracy for cycle length errors in clock signals.
Innovation Solution
A clock error detection circuit is designed with a cycle signal generation circuit, delay circuits, a holding circuit, and determination circuits to detect errors in cycle length by comparing the original cycle signal with delayed signals, eliminating the need for a high-speed clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-speed clock signal and counter are used to measure the duration of high level output state, then the detection accuracy can be improved, but the circuit configuration becomes complex
Solution Approach 1:
The patent extracts the measurement function from the time domain (using high-speed clock and counter) to the level domain (comparing signal levels). Instead of measuring how long a signal stays high, the invention compares the level of the cycle signal with the level of the delayed signal at a specific moment, eliminating the need for high-speed timing components while maintaining detection accuracy.
Solution Approach 2:
The patent replaces the mechanical counting system (counter counting pulses of high-speed clock) with a logical comparison system. The determination circuit compares logic levels of signals instead of mechanically counting pulses, substituting a complex timing mechanism with a simpler logical operation that achieves the same detection goal.
2Measurement precision
If a high-speed clock signal is prepared separately to count pulses, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The delay circuit serves multiple functions: it provides the necessary time shift for error detection and also acts as the measurement reference. The determination circuit universally compares signal levels to detect both short cycle errors and long cycle errors, eliminating the need for separate high-speed clock and counter components while maintaining measurement precision.
3Measurement precision
If the duration of high level output state is measured by counting pulses, then the detection accuracy is improved, but it requires determining in advance an allowable range for detection duration
Solution Approach 1:
Instead of measuring the duration of the high level state and comparing it to a preset threshold, the patent inverts the approach by delaying the cycle signal and comparing levels directly. This eliminates the need to pre-determine allowable detection ranges, as the delay amount naturally defines the detection window without requiring explicit threshold setting.
Data Source
AI summary
A clock error detection circuit which includes a cycle signal generation circuit that generates a cycle signal that reverses a level thereof at a start of each one cycle of a subject clock signal, a delay circuit that delays the cycle signal by a time shorter or a time longer than a prescribed cycle for the subject clock signal to output a delayed signal of the cycle signal, a holding circuit that holds a level of the delayed signal at the start of each one cycle of the subject clock signal to generate a hold signal, and a determination circuit that determines whether the level of the cycle signal matches the level of the hold signal to generate a result of the determination.