Clock Cycle Stealing for Multi-Domain Frequency Generation
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Solution Overview
Problem
Complex integrated circuits require multiple independent clock signals operating at different frequencies, which existing solutions often address by using multiple oscillators or separate phase-locked loops (PLLs), leading to inefficiencies and increased complexity.
Innovation Solution
A method and apparatus utilizing a single PLL to generate a reference clock signal, which is then divided and modified by clock divider units and cycle stealing units to produce multiple domain clock signals with varying frequencies, allowing for flexible frequency adjustment based on workload and power considerations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple oscillators or phase-locked loops (PLLs) are used to generate multiple independent clock signals for different clock domains, then each clock domain can operate independently with its own frequency, but the device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple clock signal generation functions into a single PLL by introducing a cycle stealing unit that selectively removes clock cycles from a single reference clock signal to produce multiple domain clock signals with different frequencies, eliminating the need for separate PLLs for each clock domain
Solution Approach 2:
The single PLL is made multi-functional by adding the cycle stealing unit, allowing it to serve multiple clock domains simultaneously by generating reference clock signals that are then modified to create different frequency outputs for different functional units within the integrated circuit
2Adaptability or versatility
If multiple PLLs are used to provide adjustable frequency outputs for different clock domains, then frequency flexibility is improved, but power consumption and thermal output increase
Solution Approach 1:
Multiple frequency generation functions are merged into a single PLL with a cycle stealing unit, reducing the total number of active clock generation circuits and thereby lowering overall power consumption while maintaining the ability to provide different frequencies to different clock domains
3Adaptability or versatility
If multiple PLLs are implemented on an integrated circuit die, then independent clock signal generation is achieved, but the area occupied on the die increases
Solution Approach 1:
The patent merges the functionality of multiple PLLs into a single PLL combined with a cycle stealing unit, significantly reducing the die area required for clock signal generation while maintaining the capability to provide independent, adjustable frequency outputs to multiple clock domains
Data Source
AI summary
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.