Clock-Data Alignment Using Data Delay at Multi-Gigahertz Speeds
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Solution Overview
Problem
High-speed clock-data adjustment systems face challenges in achieving a wide range of adjustment and preserving high output amplitude, particularly at speeds like 25 GHz, where traditional clock adjustment methods are inadequate due to stringent jitter and amplitude requirements.
Innovation Solution
The system adjusts data output delay rather than clock output delay, using a phase interpolator and multiplexers to align data with the clock, allowing for a wider adjustment range and finer resolution, such as ±20 ps, while maintaining high output amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional clock adjustment methods are used, then clock-output alignment is achieved, but the adjustment range is limited and output amplitude degrades at high speeds
Solution Approach 1:
Instead of adjusting the clock signal to align with data, the patent inverts the approach by adjusting the data signal to align with the clock. This is achieved by inserting delay elements in the data path controlled by selection signals, allowing the data to be retarded relative to the clock without affecting the clock signal integrity or amplitude.
Solution Approach 2:
The data path is segmented into multiple parallel paths with different delay elements. Each path has controllable delay stages that can be selectively activated. This segmentation allows for fine-grained adjustment of data timing by combining different delay paths, achieving precise alignment with the clock while maintaining signal amplitude.
2Measurement precision
If data adjustment is implemented, then alignment resolution is improved, but device complexity increases
Solution Approach 1:
The patent implements adjustment in discrete steps rather than continuous adjustment. Multiple delay elements provide adjustment ranges exceeding typical requirements (e.g., ±20 ps at 25 GHz), allowing selective activation of only the necessary delay stages. This partial action approach achieves high resolution alignment while keeping the active circuitry minimal.
Solution Approach 2:
Selection signals act as intermediaries between the clock signal and the data adjustment mechanism. These control signals selectively enable or disable specific delay elements in the data path, providing precise control over data timing without requiring direct complex interaction between clock and data adjustment circuits.
Data Source
AI summary
A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.