Clock and Data Delay Alignment for High-Speed Memory Input
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Solution Overview
Problem
Variations in temperature and voltage cause phase shift problems in clock signals, leading to increased error rates in memory circuits during data sampling.
Innovation Solution
A data input device comprising an input circuit, training circuit, detection circuit, data delay line, and clock delay line, which dynamically adjusts delay settings based on real-time detection of delay cell time slots to correct skew caused by temperature and voltage variations, ensuring accurate alignment of clock and data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are used as timing reference in memory circuits, then data sampling operation can be performed, but phase shift caused by temperature and voltage variations increases error rate
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit continuously monitors the actual clock cycle duration and compares it against expected values. Based on this feedback, the training circuit dynamically adjusts the delay settings in the data delay line and clock delay line to compensate for phase shifts caused by temperature and voltage variations, thereby maintaining accurate data sampling despite environmental changes
Solution Approach 2:
The patent transitions from static delay settings to dynamic adjustment capabilities. The training circuit can modify the delay amounts in real-time based on detected clock cycle variations. This dynamic adaptation allows the system to counteract phase shifts caused by temperature and voltage changes, maintaining reliable data sampling accuracy under varying operating conditions
2Manufacturing precision
If delay settings are adjusted to correct skew, then clock and data signal alignment improves, but transmission speed may be affected
Solution Approach 1:
The patent applies preliminary action by performing training operations before normal data transmission begins. During the training phase, the system establishes optimal delay settings based on initial clock cycle detection. These pre-configured delays ensure proper signal alignment is achieved before high-speed data transmission starts, allowing the system to maintain both precision and speed during actual operation
Solution Approach 2:
The patent uses partial action by applying delay compensation only to the extent necessary to correct skew caused by environmental variations. Rather than applying maximum delay adjustment, the system calculates and applies only the minimal required delay compensation based on detected clock cycle variations, thereby maintaining high-speed transmission while achieving sufficient signal alignment precision
Data Source
AI summary
A data input device includes an input circuit, a training circuit, a detection circuit, a data delay line and a clock delay line. The input circuit is configured to receive a first data signal and a first clock signal. The training circuit is configured to set a first delay setting based on the first data signal and the first clock signal. The detection circuit is configured to set a second delay setting based on the first delay setting and a clock cycle of the first clock signal. The second delay setting includes a second data delay amount and a second clock delay amount. The data delay line is configured to output a second data signal based on the first data signal and the second delay setting. The clock delay line is configured to output a second clock signal based on the first clock signal and the second delay setting.