Clock and Data Overlay in Emulation for Coherent Breakpoint State
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Solution Overview
Problem
Conventional hardware emulation systems require serial evaluation of clocks and data inputs, leading to slowed emulation speed and inefficiencies due to the need for clocks to fully propagate before evaluating sequential elements.
Innovation Solution
Overlaying derived clocks and data flop/latch evaluation in an emulated design allows for parallel evaluation, with the clock cone being reverted to its previous state at breakpoints to provide a coherent view of the design, enabling observability and controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clocks are fully propagated before evaluating sequential elements in conventional hardware emulation systems, then clock stability and correctness are ensured, but emulation speed is slowed down and efficiency is reduced
Solution Approach 1:
The patent pre-calculates and stores the minimum delay value among all clock paths before emulation begins. This preliminary action allows the system to quickly determine when all clocks have stabilized without requiring sequential waiting during emulation cycles, thus maintaining clock stability while improving emulation speed.
Solution Approach 2:
The patent introduces dynamic control mechanisms including a delay controller that adjusts clock delays based on emulation phase, and a pause controller that selectively pauses clock propagation or data evaluation. This dynamic control allows the system to optimize the timing relationship between clock propagation and sequential element evaluation, resolving the contradiction between ensuring clock stability and maintaining high emulation speed.
2Reliability
If clocks and data inputs are evaluated serially in conventional hardware emulation systems, then evaluation correctness is maintained, but emulation performance and throughput are reduced
Solution Approach 1:
The patent employs dynamic control mechanisms including a pause controller that can selectively pause either clock propagation or data evaluation based on the current emulation phase. This dynamic approach allows the system to maintain correct evaluation sequencing while enabling parallel processing capabilities, thus improving emulation performance without sacrificing evaluation correctness.
Solution Approach 2:
The patent segments the emulation process into distinct phases (clock propagation phase and data evaluation phase) with clear boundaries controlled by the pause controller. This segmentation allows each phase to be optimized independently while ensuring correct overall evaluation, resolving the contradiction between maintaining evaluation correctness and improving emulation performance.
3Productivity
If parallel evaluation of clocks and data is implemented in hardware emulation systems, then emulation speed is increased, but observability and controllability at breakpoints become problematic
Solution Approach 1:
The patent inverts the conventional approach by allowing parallel evaluation of clocks and data to proceed simultaneously, then using a pause controller to freeze the emulation state at breakpoints. This inversion maintains the speed benefits of parallel evaluation while restoring observability and controllability by capturing the coherent state of both clocks and data at the breakpoint moment.
Solution Approach 2:
The patent implements feedback mechanisms where the pause controller monitors breakpoint conditions and dynamically adjusts the emulation process. When a breakpoint is detected, the controller provides feedback to pause both clock propagation and data evaluation, ensuring that the design is presented in a coherent state for observation and control, thus maintaining ease of operation alongside high emulation speed.
Data Source
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AI summary
The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed. Moreover, during cycle K+1 of the emulation, the values of the sequential elements are computed based cycle K values of the clocks. When the emulation is halted due to a break, the clock cone is reverted to its previous state. This Abstract is not intended to limit the scope of the claims.