Clock Data Recovery Circuit Using Deglitch Filter and Timer
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Solution Overview
Problem
Implementing data communication across high-noise, high-voltage isolated gate driver environments is challenging due to design constraints such as common mode transient immunity, data throughput, propagation delay, power consumption, and silicon area, particularly in applications like electric vehicles and hybrid-electric vehicles, where existing solutions are often silicon area intensive, power hungry, and noise sensitive.
Innovation Solution
A clock data recovery circuit that combines clock and data into a single signal, using a modulator, isolation capacitor, and demodulator, with a deglitch filter and timer circuit to identify logic ones and zeros based on pulse duration, reducing circuit area and power consumption by eliminating the need for a delay-locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop is used for clock data recovery, then signal integrity is maintained, but silicon area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the delay-locked loop component from the clock data recovery circuit, replacing it with a simplified timer circuit that achieves the same functionality with reduced silicon area and lower power consumption while maintaining signal integrity in high-noise automotive environments
Solution Approach 2:
The patent employs a disposable, simple timer circuit structure that replaces the complex, expensive delay-locked loop, achieving adequate performance for automotive applications without requiring the overhead of sophisticated synchronization mechanisms
2Reliability
If a delay-locked loop is used for clock data recovery, then signal integrity is maintained, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry delay-locked loop from the circuit and replaces it with a low-power timer circuit that maintains signal integrity through simplified pulse duration comparison, significantly reducing power consumption in automotive gate driver applications
Solution Approach 2:
The patent uses a simple, low-cost timer circuit structure that consumes minimal power compared to the complex delay-locked loop, achieving adequate signal integrity for automotive applications without the high power overhead
3Reliability
If noise filtering is increased to handle high-noise environments, then common mode transient immunity is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The patent extracts the essential noise filtering function from complex filtering circuits and implements it through a simple timer circuit that compares pulse durations, achieving high common mode transient immunity in automotive environments without adding circuit complexity or power consumption
Solution Approach 2:
The patent changes the approach to noise filtering by using pulse duration comparison instead of traditional filtering methods, adjusting the timer threshold to differentiate valid data pulses from noise transients, thereby achieving high common mode transient immunity with simple circuitry
Data Source
AI summary
A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.