Clock and Data Recovery Circuit with Parallel Dual Control Paths
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Solution Overview
Problem
Conventional clock and data recovery circuits face challenges in stability and efficiency due to a single control path, which makes it difficult to adjust and optimize the proportional and integration gains, leading to increased costs and reduced efficiency.
Innovation Solution
A clock and data recovery circuit with parallel dual control paths, comprising a phase detecting circuit, first and second charge pumps, proportional and integration load circuits, and a voltage control oscillating circuit, where the phase detecting circuit generates proportional and integration control signals to independently control the currents injected into separate load circuits, producing proportional and integration voltages to adjust the clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single control path is used to control both proportional and integration gains, then the circuit structure is simple, but it is difficult to adjust and optimize the gains independently, leading to reduced efficiency and increased costs
Solution Approach 1:
The patent divides the single control path into two separate parallel control paths: one for proportional gain control and another for integration gain control. This segmentation allows independent adjustment and optimization of each gain parameter, resolving the contradiction between ease of adjustment and circuit complexity by organizing the control functions into distinct, manageable segments.
2Speed
If the resistance R is increased to raise proportional gain, then the phase response speed improves, but the integration gain also increases which may cause frequency adjustment to be too sensitive
Solution Approach 1:
The patent segments the control paths so that proportional gain and integration gain are controlled independently through separate circuits. This allows the proportional gain to be optimized for fast phase response while the integration gain can be separately tuned to maintain frequency adjustment stability, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent enables independent adjustment of proportional and integration gain parameters through separate control paths. This parameter independence allows optimization of phase response speed through proportional gain while maintaining frequency adjustment stability through separate integration gain control, resolving the trade-off between these two parameters.
3Reliability
If the capacitance C is increased to reduce integration gain, then frequency adjustment stability improves, but the proportional gain also changes requiring re-adjustment of resistance
Solution Approach 1:
The patent segments the control into independent proportional and integration paths, allowing capacitance C to be adjusted for frequency stability without affecting proportional gain. The separate control paths eliminate the coupling effect that would otherwise require re-adjustment of resistance, resolving the contradiction between reliability and adjustment complexity.
4Reliability
If larger resistance R or capacitance C is used to improve stability factor, then the system stability improves, but the circuit cost increases
Solution Approach 1:
The patent segments the control paths to enable independent optimization of proportional and integration gains. This segmentation allows the system to achieve improved stability factor through optimized control parameters rather than simply increasing component values, thereby improving reliability without proportionally increasing circuit cost.
Solution Approach 2:
The patent optimizes system stability by changing control parameters (gains) rather than increasing physical component values. The independent adjustment of proportional and integration gains allows achieving better stability factor through parameter optimization, reducing the need for larger resistance or capacitance values and thus controlling circuit cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances stability and reduces signal jitter, allowing for easier optimization and improved efficiency by separating the proportional and integration control paths, enabling independent adjustment of each stage circuit and gain, thus improving the overall performance of the clock and data recovery circuit.
Implementation Method 1
the phase detecting circuit compares a phase difference between the data signal and a plurality of clock signals to generate two proportional control signals and two integration control signals
Implementation Method 2
The first current IP and the second current II are respectively injected into the proportional load circuit and the integration load circuit to generate a proportional voltage VP and an integration voltage VI
Implementation Method 3
the voltage control oscillating circuit adjusts a phase and a frequency of the plurality of clock signals in response to the proportional voltage VP and an integration voltage VI
Data Source
AI summary
A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between a data signal and a plurality of clock signals to generate two proportional control signal and two integration control signal for respectively controlling the first charge pump and the second charge pump to generate a first current and a second current. The proportional load circuit and the integration load circuit respectively receive the first current and the second current to output a proportional voltage and an integration voltage. The voltage control oscillating circuit adjusts the phase and frequency of the plurality of clock signals in response to the proportional voltage and the integration voltage.