Clock Data Recovery Circuit Equalizer Calibration

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Solution Overview

Problem

High-speed signaling systems face challenges in reducing latent signal distortions, particularly reflection-type ISI, which require a large number of taps and increase parasitic capacitance, degrading frequency response and potentially worsening impedance discontinuities.

Innovation Solution

A signaling system with a selectable-tap equalizer that uses pre-emphasis and receive-side equalization, where the receiver buffers data for parallel transfer, allowing selected stored data values to counteract reflections without additional storage, reducing the number of equalizer taps needed and minimizing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of equalizer taps are used to counteract reflection-type ISI, then the ability to reduce high-latency distortions is improved, but parasitic capacitance increases and frequency response degrades

Engineering Contradiction:

Improveability to reduce high-latency distortionsVSAvoidparasitic capacitance and frequency response degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the equalization function into two separate components: a transmit-side equalizer that handles low-latency distortions (dispersion-type ISI) and a receive-side equalizer that handles high-latency distortions (reflection-type ISI). This segmentation allows each equalizer to use a small number of taps, avoiding the need for a large number of taps that would increase parasitic capacitance. The transmit-side equalizer uses pre-emphasis to mitigate dispersion-type ISI, while the receive-side equalizer uses post-cursor equalization to mitigate reflection-type ISI, thereby resolving the contradiction between reducing high-latency distortions and minimizing parasitic capacitance.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the shift register is made deeper to store more tap values, then the ability to compensate for reflections at any latency is improved, but device complexity and parasitic capacitance increase

Engineering Contradiction:

Improveability to compensate for reflections at any latencyVSAvoidshift register depth and parasitic capacitance

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the equalization task between transmit and receive sides, eliminating the need for a single deep shift register. The transmit-side equalizer uses a shallow shift register for pre-emphasis, while the receive-side equalizer uses a separate shallow shift register for post-cursor equalization. This segmentation maintains adaptability to compensate for reflections at any latency while keeping device complexity and parasitic capacitance low.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The transmit-side equalizer performs preliminary action by applying pre-emphasis to the transmitted signal to pre-compensate for expected dispersion-type ISI and reduce the burden on the receive-side equalizer. This preliminary action allows the receive-side equalizer to focus only on reflection-type ISI, reducing the required tap depth and overall system complexity.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If additional equalizing taps are added to the transmit circuit, then the ability to reduce dispersion-type ISI is improved, but impedance discontinuity increases and frequency response degrades

Engineering Contradiction:

Improveability to reduce dispersion-type ISIVSAvoidimpedance discontinuity and frequency response degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the equalization function so that the transmit-side equalizer handles only low-latency dispersion-type ISI with a limited number of taps, while the receive-side equalizer handles high-latency reflection-type ISI. This segmentation ensures that the transmit-side equalizer does not require additional taps that would increase impedance discontinuity, thereby maintaining frequency response while still effectively reducing dispersion-type ISI.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8861667B1Clock data recovery circuit with equalizer clock calibration

Publication Date: 2014.10.14 RAMBUS INC

AI summary

A signal receiving circuit having an equalizer calibration function. The signal receiving circuit includes a sampling circuit, output driver and clock signal generator. The sampling circuit captures samples of a data signal in response to a sampling clock signal. The output driver outputs an equalizing signal to an input of the sampling circuit in response to a first clock signal. The clock signal generator adjusts a phase of the first clock signal to achieve phase alignment between transitions of the equalizing signal and transitions of the data signal.