Clock Data Recovery Interpolator for Satellite Doppler Shifts
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Solution Overview
Problem
Inter-satellite optical communication systems face challenges due to high Doppler shifts and sampling clock offsets caused by the relative velocity of satellites in low earth orbits and geostationary orbits, leading to signal degradation and loss of lock in Clock and Data Recovery (CDR) schemes.
Innovation Solution
A robust Clock Data Recovery (CDR) scheme is implemented using a Feedback Digital Phase Locked Loop (D-PLL) structure with an interpolator, timing error detector, loop filter, and numerically controlled oscillator, which adapts to dynamic pointing-induced fading and corrects up to ±70 ppm sampling clock offsets, ensuring stable signal recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If terrestrial coherent optical systems are used for high data rate links, then data rate is improved to 100 Gbps or higher, but the system becomes prone to large Doppler shifts and sampling clock offsets when applied to satellite systems
Solution Approach 1:
The patent implements a dynamic sampling clock adjustment mechanism that continuously adapts to Doppler shifts and clock offsets. The system uses a feedback loop with a timing error detector and numerically controlled oscillator to dynamically correct sampling instants, enabling the terrestrial coherent optical system to maintain signal stability despite large frequency variations in satellite communications
Solution Approach 2:
The system changes the sampling clock frequency parameter in real-time to compensate for Doppler effects. By adjusting the sampling rate and timing instants based on detected errors, the system maintains proper synchronization despite the large frequency shifts inherent in satellite-to-satellite and satellite-to-ground communications
2Adaptability or versatility
If satellites travel at high relative velocity to enable inter-satellite links, then connectivity is improved, but large Doppler shifts and sampling clock offsets occur causing signal degradation
Solution Approach 1:
The patent employs a feedback-based Clock Data Recovery system where the timing error detector continuously monitors sampling instants and feeds back correction signals to the numerically controlled oscillator. This closed-loop feedback mechanism automatically compensates for Doppler shifts and clock offsets caused by high relative satellite velocities, maintaining signal quality despite the necessary high-speed motion for inter-satellite connectivity
Solution Approach 2:
The system dynamically adjusts sampling parameters in real-time based on the relative motion between satellites. The numerically controlled oscillator and interpolator continuously modify sampling instants to track the changing frequency conditions, enabling the system to maintain reliable communication despite high relative velocities required for inter-satellite links
Data Source
AI summary
A clock data recovery (CDR) apparatus can include an interpolator circuitry to interpolate an input received signal and to generate an output signal removing the sampling clock offsets. The apparatus can include timing error detector (TED) circuitry coupled to process the output signal and to provide a timing error as feedback to the interpolator circuitry, the timing error being adjusted by gain factors used in at least one of an automatic gain control (AGC) circuitry and an orthogonalization circuitry. The apparatus can include loop filter (LF) circuitry to filter the timing error to remove noise effects. The apparatus can include numerically controlled oscillator (NCO) circuitry to adjust for a basepoint and fractional interval used to adjust resampling coefficients within the interpolator circuitry.