Clock Data Recovery Circuit Using Multiphase Oversampling
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Solution Overview
Problem
Conventional clock data recovery (CDR) circuits face challenges with increased chip size, power consumption, and complexity as data transmission rates rise, particularly due to high-frequency voltage-controlled oscillators (VCOs) and wiring-induced clock delays, which complicate circuit design and reduce reusability.
Innovation Solution
A data recovery method and circuit that oversample serially transmitted data using a multiphase clock with a frequency at or below the input data clock frequency, allowing for accurate recovery independent of the data transmission clock and reducing the impact of jitter, thereby simplifying high-speed data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency VCO is used in conventional CDR circuits to match high data transmission rates, then data transmission speed is improved, but chip size and power consumption increase
Solution Approach 1:
The patent segments the clock recovery process by using a lower-frequency clock (f2) that is a fraction of the data transmission rate (f1), rather than using a single high-frequency VCO. The multiphase clock generator divides the high-frequency data clock into multiple lower-frequency phases, reducing the VCO frequency requirement while maintaining synchronization capability.
Solution Approach 2:
The patent employs dynamic phase shifting of the multiphase clock generator to adapt to frequency differences between the data transmission clock and the recovered clock. The phase adjustment mechanism allows the system to dynamically synchronize data recovery despite frequency variations, enabling operation at high data rates while using a lower-frequency VCO.
2Speed
If a high-frequency VCO is used in conventional CDR circuits to match high data transmission rates, then data transmission speed is improved, but chip size increases
Solution Approach 1:
The patent segments the clock recovery process by using a lower-frequency clock (f2) that is a fraction of the data transmission rate (f1), rather than using a single high-frequency VCO. The multiphase clock generator divides the high-frequency data clock into multiple lower-frequency phases, reducing the VCO frequency requirement while maintaining synchronization capability.
Solution Approach 2:
The patent employs dynamic phase shifting of the multiphase clock generator to adapt to frequency differences between the data transmission clock and the recovered clock. The phase adjustment mechanism allows the system to dynamically synchronize data recovery despite frequency variations, enabling operation at high data rates while using a lower-frequency VCO.
3Speed
If high-frequency VCO is used in conventional CDR circuits, then data transmission speed is improved, but wiring-induced clock delay becomes significant
Solution Approach 1:
The patent segments the clock recovery process by using a lower-frequency clock (f2) that is a fraction of the data transmission rate (f1), rather than using a single high-frequency VCO. The multiphase clock generator divides the high-frequency data clock into multiple lower-frequency phases, reducing the VCO frequency requirement while maintaining synchronization capability.
Solution Approach 2:
The patent employs dynamic phase shifting of the multiphase clock generator to adapt to frequency differences between the data transmission clock and the recovered clock. The phase adjustment mechanism allows the system to dynamically synchronize data recovery despite frequency variations, enabling operation at high data rates while using a lower-frequency VCO.
4Measurement precision
If conventional CDR circuits are redesigned for each process due to wiring delay variations, then data recovery accuracy is maintained, but reusability is degraded
Solution Approach 1:
The patent segments the clock recovery process by using a lower-frequency clock (f2) that is a fraction of the data transmission rate (f1), rather than using a single high-frequency VCO. The multiphase clock generator divides the high-frequency data clock into multiple lower-frequency phases, reducing the VCO frequency requirement while maintaining synchronization capability.
Solution Approach 2:
The patent employs dynamic phase shifting of the multiphase clock generator to adapt to frequency differences between the data transmission clock and the recovered clock. The phase adjustment mechanism allows the system to dynamically synchronize data recovery despite frequency variations, enabling operation at high data rates while using a lower-frequency VCO.
Data Source
AI summary
A data recovery method includes the steps of:(a) oversampling data that have been transmitted serially in sync with a first clock of frequency f1, using a multiphase clock generated by shifting a phase of a second clock of frequency f2 at a prescribed interval, the second frequency f2 of the multiphase clock being at or below the first frequency f1; (b) extracting f1/f2 bits on average from the oversampled data; and(c) recovering the extracted bits to restore the received data.