Clock Data Recovery Circuit Phase Correction
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Solution Overview
Problem
Conventional clock data recovery circuits face challenges in maintaining synchronization between clock and data signals, particularly when data is not transitioning frequently, leading to increased jitter and reduced efficiency due to the need for dummy bit insertion, which affects the frequency range and timing skew.
Innovation Solution
A clock data recovery circuit that generates multiple regenerated clock signals with phases differing by half a cycle, using a latch circuit, comparison circuit, logical sum signal generating circuit, and charge pump to correct phases and minimize jitter, allowing improved followability of clock signals to data transitions while reducing dummy bit insertion frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy bits are inserted frequently to ensure data transitions, then synchronization is maintained, but data transfer efficiency deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the charge pump continuously monitors phase differences between clock and data signals and adjusts the VCO frequency accordingly. This allows the system to maintain synchronization without relying on frequent dummy bit insertion, as the phase comparison circuit detects actual data transitions and corrects timing skew dynamically, thereby maintaining reliability while improving data transfer efficiency.
Solution Approach 2:
The patent dynamically changes the frequency parameter of the VCO based on phase comparison results. By adjusting the VCO frequency in response to detected phase differences, the system adapts to varying data transition patterns without requiring fixed-frequency operation or frequent dummy bits, thus maintaining synchronization while preserving data transfer efficiency.
2Productivity
If dummy bits are inserted at lower frequency to prolong data non-transition periods, then data transfer efficiency improves, but the difference in electron charge amount charged with the charge pump increases
Solution Approach 1:
The patent employs dynamic adjustment of the charge pump output based on real-time phase comparison results. The charge pump voltage is continuously modulated according to the detected phase difference, allowing the electron charge amount to adapt to the actual data transition frequency. This dynamic control prevents excessive charge accumulation while ensuring sufficient charging during transitions, thereby improving data transfer efficiency without causing large variations in electron charge amount.
3Adaptability or versatility
If the charge pump charges a large amount of electron charge, then the clock follows data pattern changes better, but jitter of the clock increases
Solution Approach 1:
The phase comparison circuit provides continuous feedback to the charge pump, enabling precise control of the electron charge amount. The feedback mechanism ensures that the charge pump supplies just enough charge to correct phase differences without overcharging, which would cause excessive frequency adjustments and increase jitter. This balanced feedback control maintains good clock follow ability while minimizing jitter.
Solution Approach 2:
The patent applies partial action by charging only the necessary amount of electrons required to correct the detected phase difference. Rather than continuously charging at maximum rate, the charge pump operates proportionally to the actual timing skew, providing sufficient correction without excessive charge that would cause frequency instability and increased jitter.
4Reliability
If the charge pump charges a small amount of electron charge, then clock jitter is reduced, but the clock cannot follow data pattern changes
Solution Approach 1:
The feedback mechanism ensures that the charge pump responds appropriately to the magnitude of phase differences. When timing skew is large, the feedback signal triggers larger charge amounts to correct the phase quickly. When timing skew is small, the charge amount is reduced to maintain stability. This adaptive feedback control allows the clock to follow data pattern changes effectively while keeping jitter minimal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the ability of the clock to follow data transitions while minimizing jitter, thereby improving data transmission efficiency and extending the period when data is not transitioning, without significant increases in jitter or frequency adjustments.
Implementation Method 1
The charge pump is configured to supply a charge pump voltage having an electron charge amount corresponding to a comparison result to the VCO
Implementation Method 2
The VCO is configured to change an oscillation frequency according to the charge pump voltage, so that the VCO corrects a phase of the regenerated clock
Data Source
AI summary
A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal, and to generate a regenerated clock signal. The clock data recovery circuit includes a regenerated clock generating circuit; a latch circuit; a comparison circuit; a logical sum signal generating circuit; and a charge pump.