Clock and Data Recovery Circuit Using Phase Difference Selector
Solution Overview
Problem
Modern clock and data recovery circuits face challenges due to increased data speeds, requiring complex designs, additional circuitry, and high power consumption, which also occupy a large footprint in integrated circuits.
Innovation Solution
A clock and data recovery circuit that generates multiple clock signals with the same frequency but different phases, using a phase difference selector and phase detectors to align these signals with the data signal, eliminating the need for phase interpolators or rotators, thus simplifying design, reducing power usage, and minimizing footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clock and data recovery circuits are used to handle increased data speeds, then data transmission capability is improved, but circuit complexity and power consumption increase significantly
Solution Approach 1:
The circuit segments the high-speed data sampling task into multiple lower-frequency clock domains. By generating multiple clock signals at fractions of the data rate with different phases, the circuit divides the sampling responsibility across multiple clock cycles, thereby reducing the frequency requirement and complexity of individual clock circuits while maintaining the ability to sample multiple data bits.
Solution Approach 2:
The circuit dynamically adjusts the phase of clock signals to optimize sampling timing. By selectively combining clock signals with different phases based on detected phase differences, the circuit adapts to varying data signal conditions and achieves optimal sampling points without requiring a single high-frequency clock circuit.
2Speed
If traditional clock and data recovery circuits are used to handle increased data speeds, then data transmission capability is improved, but power consumption increases
Solution Approach 1:
The power consumption is segmented across multiple lower-frequency clock circuits instead of concentrating it in a single high-frequency clock circuit. Each clock circuit operates at a manageable frequency fraction of the data rate, reducing the instantaneous power demand while collectively achieving the required sampling throughput for high-speed data transmission.
Solution Approach 2:
The circuit uses periodic phase detection and adjustment cycles to maintain synchronization. By periodically detecting phase differences and adjusting clock phases rather than continuously operating at full power, the circuit reduces average power consumption while maintaining the ability to track and sample high-speed data signals.
3Speed
If traditional clock and data recovery circuits are used, then data transmission capability is improved, but footprint area increases
Solution Approach 1:
The circuit footprint is segmented into multiple functional blocks operating at lower frequencies. By distributing the sampling function across multiple clock domains and using shared phase detection and control logic, the total area required is reduced compared to implementing a single high-frequency clock and data recovery circuit with all functionality integrated.
4Productivity
If multiple clock signals with different phases are generated, then sampling efficiency is improved, but phase alignment complexity increases
Solution Approach 1:
The circuit uses feedback from phase detection to automatically adjust and align the phases of multiple clock signals. By continuously detecting phase differences between clock signals and the data signal, and using this information to adjust clock phases, the circuit achieves accurate phase alignment without requiring complex manual configuration or calibration circuits.
Solution Approach 2:
The circuit introduces phase detection and control logic as intermediary elements between the multiple clock signals and the data sampling function. These intermediaries automatically manage the phase alignment of multiple clock signals, simplifying the overall system by centralizing the complexity in dedicated phase control blocks rather than distributing it throughout the sampling circuitry.
Data Source
AI summary
A circuit may include a phase difference selector, a clock signal generator, a reference clock phase detector, and a data signal phase detector. The phase difference selector may be configured to select one of multiple reference clock phase difference signals generated by the reference clock phase detector based on a difference in phase between multiple clock signals and a reference clock. The clock signal generator may be configured to generate the multiple clock signals based on the selected reference clock phase difference signal. The data signal phase detector may be configured to generate a data phase difference signal based on differences in phase between the clock signals and a data signal. The data phase difference signal may be used by the phase difference selector to select one of the reference clock phase difference signals.