Clock Data Recovery Circuit Timer Slope Adjustment
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Solution Overview
Problem
Conventional clock recovery systems in automotive CAN networks with low-accuracy oscillators struggle to accurately recover period errors exceeding ±5% over a wide temperature range, often requiring feed-forward error compensation, which is resource-intensive and limited in accuracy.
Innovation Solution
A clock data recovery circuit that decodes synchronization frames, measures the time between consecutive falling edges, and adjusts the timer slope using integer values validated by a CRC check, allowing for oscillator period error correction up to ±10% without feed-forward compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If feed-forward error compensation is used to recover oscillator period deviation, then clock recovery accuracy is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent implements a feedback mechanism where the measured time between consecutive falling edges is used to adjust the timer slope correction for subsequent measurements. The system continuously monitors the period error and dynamically adjusts the slope correction value, creating a closed-loop feedback system that improves clock recovery accuracy without requiring complex feed-forward compensation tables or additional hardware resources.
2Measurement precision
If feed-forward error compensation with linear interpolation is used, then clock recovery accuracy is improved, but the system requires additional memory resources and processing overhead
Solution Approach 1:
The patent extracts only the essential correction information needed for clock recovery by directly measuring the time between consecutive falling edges and using this measurement to adjust the timer slope. This eliminates the need for storing large interpolation tables in OTP memory, removing the memory resource burden while maintaining the core functionality of error compensation.
Solution Approach 2:
The system uses the incoming signal itself to provide the correction information needed. By measuring the time between falling edges directly from the received signal and using this measurement to adjust the timer slope, the system serves its own calibration needs without requiring external pre-programmed correction tables or additional memory resources.
3Device complexity
If conventional frequency locking is used, then device complexity is minimized, but clock recovery accuracy deteriorates for period errors exceeding ±5%
Solution Approach 1:
The patent changes the operational parameter of the timer by dynamically adjusting its slope based on measured period errors. Instead of using a fixed frequency locking mechanism, the system modifies the timer slope correction parameter in response to measured deviations, enabling accurate recovery of period errors up to ±10% while maintaining relatively simple circuitry without complex feedback loops or additional compensation hardware.
Data Source
AI summary
An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.