Clock Data Restoration Device for Jitter Mitigation
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Solution Overview
Problem
Conventional clock data restoration devices fail to reliably restore clock signals and data in the presence of substantial transmitter clock jitter and intersymbol interference.
Innovation Solution
A clock data restoration device comprising an equalizer, sampler, clock generator, equalizer controller, and phase monitor, which adjusts the high-frequency component of the digital signal and synchronizes the clock signals to minimize phase differences, thereby stabilizing clock signal and data restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock data restoration devices are used, then device complexity is kept simple, but reliability deteriorates when substantial transmitter clock jitter and intersymbol interference are present
Solution Approach 1:
The equalizer performs preliminary action by adjusting the high-frequency component level of the digital signal before sampling occurs. This pre-processing compensates for waveform deterioration and intersymbol interference in advance, ensuring that when the sampler detects the signal, the transitions are sharp and well-defined, thereby improving restoration reliability without requiring complex post-processing circuits
Solution Approach 2:
The equalizer controller implements feedback by detecting sampling results and using this information to adjust the equalizer's high-frequency component amplification level. This closed-loop control adapts to varying signal conditions and transmitter clock jitter, maintaining reliable restoration across different operating conditions while keeping the overall device structure manageable
2Measurement precision
If the high frequency component level is adjusted by an equalizer, then measurement precision of data transitions is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The equalizer controller performs multiple functions using a single integrated circuit: it detects sampling results, determines appropriate equalization levels, controls the equalizer's high-frequency amplification, and monitors overall signal quality. This multi-functionality improves measurement precision while avoiding the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity
3Measurement precision
If three timing detections are performed for each bit data, then measurement precision is improved, but productivity decreases due to increased processing time
Solution Approach 1:
The equalizer performs preliminary action by pre-adjusting the digital signal's high-frequency components before the three-timing detection process. This pre-enhancement of signal edges ensures that transitions are sharp and well-defined, allowing the three timing detections to quickly and accurately identify the central timing without requiring extensive processing or multiple iteration cycles, thereby maintaining productivity
Data Source
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AI summary
A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.