Clock-Decoded DFE Receiver for High-Speed LPDDR4 Signals
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Solution Overview
Problem
Current low power double data rate (LPDDR4) random access memory (RAM) faces challenges in achieving high data rates due to low power supply levels, inter-symbol interference, clock jitter, and crosstalk, which degrade input signal quality and limit the performance of traditional sense-amplifier latches, especially at higher speeds like 6400 Mbps.
Innovation Solution
Implementing a multi-tap decision feedback equalization (DFE) circuit with a minimal length digital decision feedback loop and using static analog signals, where the clocked receiver includes identical data latches with different analog unbalances and a decision-based clock decoder to activate only the appropriate latch, and combining outputs to drive the final output, thereby minimizing feedback loop latency and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sense-amplifier latches are used, then device simplicity is maintained, but speed and reliability deteriorate at high data rates
Solution Approach 1:
The patent implements decision feedback equalization (DFE) where the output of the data latch is fed back through a feedback path to compensate for inter-symbol interference. The feedback signal is combined with the input signal before the latch decision, effectively canceling ISI and improving signal quality at high data rates.
Solution Approach 2:
The patent divides the feedback path into multiple taps, where each tap processes a different previous bit contribution to the ISI. This segmentation allows selective compensation of interference from different time delays, improving equalization precision without requiring full digital processing of all previous bits.
2Measurement precision
If full digital DFE is implemented, then equalization precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a hybrid approach where only the feedback path is digitized into multiple taps, while the core data latch remains analog. This segmentation allows precise ISI compensation through digital feedback coefficients while maintaining the speed and simplicity of analog latching operation.
Solution Approach 2:
The patent applies digital processing selectively to the feedback path where precision is most needed for ISI cancellation, while keeping the main data path analog for speed. This local application of digital precision optimizes the trade-off between equalization accuracy and overall circuit complexity.
3Speed
If analog feedback loop is used, then device complexity is reduced, but speed is limited by bandwidth and latency
Solution Approach 1:
The patent replaces the traditional continuous analog feedback loop with a discrete digital feedback structure. Instead of using analog circuits to generate feedback, the patent uses digital logic to compute feedback coefficients and generate feedback signals, eliminating analog bandwidth and latency limitations.
Solution Approach 2:
The patent structures the feedback loop to operate in discrete phases synchronized with the clock cycles. The feedback is updated periodically at each bit period, allowing precise timing control and avoiding the continuous analog loop delays that limit receiver speed.
4Reliability
If DFE is implemented to compensate for ISI, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent divides the feedback into multiple taps that can be selectively enabled. Not all taps need to be active simultaneously, allowing power consumption to be adjusted by enabling only the necessary number of taps based on channel conditions, thus reducing overall power usage while maintaining signal quality.
Solution Approach 2:
The patent allows dynamic adjustment of feedback coefficients and tap weights based on channel conditions. By adapting the strength and number of active feedback taps, the system optimizes the balance between signal quality improvement and power consumption, using stronger feedback only when channel degradation is severe.
Data Source
AI summary
Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.