Clock Dejitter Controller Using Phase-Locked Loop for Data Transmission
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Solution Overview
Problem
Current communication systems face challenges in generating a sending clock that matches varying data frequencies during free scheduling, leading to increased bit error rates and instability due to significant clock jitter, especially in remote service scenarios where local clock synchronization is required.
Innovation Solution
A clock dejitter method and apparatus that dynamically adjusts the sending clock using a phase lock loop and frequency conversion module, in conjunction with a FIFO buffer area, to track variations in the data enable signal and stabilize the sending clock in real-time, ensuring it aligns with the system clock and data sending state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed ratio method is used to generate the sending clock, then the system structure is simple, but the clock jitter increases significantly when data frequency changes, leading to increased bit error rate and difficulty in frequency locking
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed ratio clock generation method to a dynamic phase-lock loop (PLL) based method. The PLL continuously adjusts the sending clock frequency to track the system clock frequency variations, enabling the system to adapt to changing data frequencies while maintaining synchronization and reducing clock jitter.
Solution Approach 2:
The patent implements feedback through the phase-lock loop mechanism, where the generated sending clock is continuously compared with the system clock, and the frequency adjustment is based on the phase difference feedback. This closed-loop feedback system ensures the sending clock remains synchronized with the data frequency changes, significantly reducing bit error rate.
2Adaptability or versatility
If the sending frequency of service data changes significantly, then the free scheduling ability is improved, but the clock jitter exceeds the allowable range, causing data drift and transmission failure
Solution Approach 1:
The patent uses dynamic frequency tracking through the phase-lock loop to maintain clock synchronization stability even when data frequency changes significantly. The PLL dynamically adjusts the sending clock frequency to match the system clock, preventing clock jitter from exceeding allowable ranges while enabling flexible free scheduling of service data.
Solution Approach 2:
The patent changes the frequency parameter of the sending clock dynamically based on system clock variations. By continuously adjusting the sending clock frequency to track the system clock, the system maintains stable clock synchronization while adapting to significant changes in data transmission requirements.
3Reliability
If a phase lock loop is used to generate the sending clock, then the clock synchronization is improved, but the device complexity increases due to additional components
Solution Approach 1:
The patent achieves universal application by integrating the phase-lock loop functionality into the clock generation module, allowing the same structure to handle various data frequency changes and scheduling requirements. This multi-functional design provides reliable clock synchronization across different operating conditions without requiring separate specialized circuits for each scenario.
4Adaptability or versatility
If remote free service scheduling is implemented, then the scheduling flexibility is improved, but the requirement for local clock generation increases system complexity and synchronization difficulty
Solution Approach 1:
The patent applies dynamics by implementing a dynamic phase-lock loop for local clock generation that automatically tracks system clock frequency variations. This dynamic approach enables remote free service scheduling with improved flexibility while managing synchronization complexity through automatic frequency adaptation rather than fixed rigid configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the free scheduling processing ability, reduces bit error rates, and improves the stability and efficiency of large capacity data switch transmission by generating a sending clock that accurately adapts to data frequency changes.
Implementation Method 1
The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks.
Implementation Method 2
The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer.
Data Source
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AI summary
The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.