Digital Clock De-Jittering Circuit for T1 and E1 Frequency Switching
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Solution Overview
Problem
Existing de-jittering methods for clock signals, such as analogue phase-locked loops and digitally controlled crystal oscillators, are complex, difficult to design, and unable to efficiently transition between T1 and E1 clock frequencies, limiting their practical application.
Innovation Solution
A de-jittering method using controllable dividers to form a digital phase-locked loop, where the clock signal is compared with a feedback clock to generate a control signal, allowing the controllable divider to produce a stable clock signal, and enabling frequency adjustment to accommodate both T1 and E1 frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analogue phase-locked loop de-jittering circuit is used, then the de-jittering performance can be guaranteed, but the circuit structure becomes complicated and difficult to design
Solution Approach 1:
The patent replaces the analogue phase-locked loop circuit with a digital de-jittering circuit that uses a controllable divider and digital logic components. This substitution of analogue mechanics with digital electronics simplifies the circuit structure while maintaining de-jittering functionality, as the digital circuit can achieve the same phase locking and jitter attenuation without the complexity of analogue components.
Solution Approach 2:
The patent changes the operating parameters by using a controllable divider that can be dynamically adjusted through digital control signals. Instead of fixed analogue frequency division, the digital circuit allows flexible parameter adjustment of division ratios and timing characteristics, enabling the same circuit to adapt to different clock frequencies (T1 and E1) and maintain optimal de-jittering performance across varying conditions.
2Reliability
If a digitally controlled crystal oscillator is used, then the de-jittering function is achieved, but the circuit is complex and unable to efficiently transition between T1 and E1 clock frequencies
Solution Approach 1:
The patent designs a universal de-jittering circuit based on controllable dividers that can handle multiple clock frequency standards (both T1 and E1). The circuit incorporates frequency identification logic and automatic configuration capabilities, allowing a single circuit design to serve multiple functions and frequency domains without requiring separate dedicated circuits for each standard.
Solution Approach 2:
The patent implements dynamic frequency transition capability by using controllable dividers that can be reconfigured in real-time. The circuit includes frequency detection and switching logic that automatically adjusts the divider configuration when transitioning between T1 and E1 clock frequencies, enabling smooth and efficient frequency changes without manual intervention or complex external control.
3Ease of manufacture
If conventional de-jittering methods are used, then the design process is difficult, but the implementation cost is high
Solution Approach 1:
The patent replaces complex analogue circuit design with digital logic design, which is generally easier to implement and manufacture. Digital circuits based on controllable dividers and standard logic components can be designed using conventional EDA tools and manufactured using standard CMOS processes, reducing both design complexity and manufacturing costs compared to precision analogue circuit implementation.
Data Source
AI summary
The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating the control signal that is then transmitted to the controllable frequency divider; the controllable frequency divider performs frequency division upon the input high-frequency signal to generate a stable clock, and the stable clock is outputted as the feedback clock signal which has been de-jittered. The present invention also discloses a de-jittering apparatus for implementing the above-mentioned method, which includes: a circuit for generating a control signal and a controllable frequency divider. By applying the present invention, the de-jittering circuit for clock signal can be simple. What's more, transition between T1 clock frequency and E1 clock frequency can also be implemented to meet practical requirements better.