Clock Delay Boundary Search for Data-Clock Skew Compensation
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Solution Overview
Problem
High-speed data transfer in semiconductor devices, particularly in portable terminals, faces challenges in maintaining stable data transfer due to skew between data and clock signals transmitted over separate lines, exacerbated by increasing data transmission rates and waveform distortion, which reduces the time margin and makes it difficult to design transmission lines effectively.
Innovation Solution
A semiconductor device with a delay circuitry and delay control circuitry that performs a calibration process to determine an optimized delay time, adjusting the phase of the clock signal to compensate for skew by searching for minimum and maximum delay times and calculating an average optimized value, thereby stabilizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission rate is increased to achieve higher speed data transfer, then productivity is improved, but the time margin for stable data transfer is reduced due to skew between data and clock signals
Solution Approach 1:
The patent implements a variable delay circuit that dynamically adjusts the delay time of the clock signal based on detected skew conditions. The delay time is not fixed but can be changed in real-time to compensate for variations in skew, allowing the system to maintain reliable data transfer even at high transmission rates where static timing margins would be insufficient.
Solution Approach 2:
The patent employs a skew detection circuit that continuously monitors the timing skew between data and clock signals and feeds this information back to control the variable delay circuit. This feedback mechanism enables automatic adjustment of the clock signal delay to maintain optimal timing margins, resolving the contradiction between high transmission rate and stable data transfer.
2Manufacturing precision
If equal-length wiring is used to compensate for transmission line length difference, then skew caused by length difference is reduced, but skew caused by frequency characteristics (ISI) remains significant at high data rates
Solution Approach 1:
The patent introduces a variable delay circuit as an intermediary element between the clock signal source and the data sampling point. This intermediary actively compensates for skew caused by frequency characteristics and ISI by adjusting the clock signal delay, providing a solution that goes beyond passive equal-length wiring to address the root cause of skew at high data rates.
3Manufacturing precision
If setup time and hold time are reduced through microfabrication to maintain time margin, then the time margin is preserved, but it becomes difficult to maintain stable data transfer at increasingly higher data transmission rates
Solution Approach 1:
Instead of relying on fixed, minimized setup and hold times achieved through microfabrication, the patent introduces a dynamic delay adjustment mechanism. The variable delay circuit can adaptively extend or reduce the clock signal delay based on actual skew conditions, providing a flexible solution that maintains timing margins without being constrained by fixed manufacturing parameters.
Data Source
AI summary
A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.