Clock Route Delay Coding for Integrally Related Frequencies
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Solution Overview
Problem
In network synchronization applications, existing technologies face challenges in accurately measuring and compensating for pin-to-pin delays in clock signals due to increased delays from additional peripheral circuits and routing mismatches on printed circuit boards, which are critical for maintaining synchronization and meeting aggressive delay budgets.
Innovation Solution
A method and integrated circuit design that measures pin-to-pin delays between clock signals with integrally related frequencies using a delay measurement circuit with a time-to-digital converter, skew circuits, and switch circuits, which generates delay codes based on time codes, skew codes, and signal periods to account for conductive path delays without requiring additional circuitry, thereby improving delay estimation and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuits (switches, multiplexers, frequency dividers) are added to provide clock signal flexibility and redundancy, then adaptability and versatility are improved, but device complexity and delay increase
Solution Approach 1:
The phase-locked loop circuit is designed to perform multiple functions: it generates output clock signals, measures pin-to-pin delays, and provides synchronization. The same PLL circuit handles both clock generation and delay measurement tasks, eliminating the need for separate dedicated measurement circuits and reducing overall device complexity while maintaining versatility
Solution Approach 2:
The system uses its own internal PLL circuit and existing clock paths to perform delay measurements without requiring external measurement equipment or additional dedicated test circuits. The PLL measures delays through its own feedback mechanism and time-to-digital converter, making the system self-sufficient for both clock generation and delay characterization
2Adaptability or versatility
If peripheral circuits are added to support multiple clock frequencies and formats, then adaptability is improved, but pin-to-pin delay increases
Solution Approach 1:
The system performs delay measurements during the calibration phase before actual clock signal distribution. By measuring and storing delay values in advance, the system compensates for the additional delays introduced by peripheral circuits, ensuring that synchronization requirements are met even with the added circuit complexity
Solution Approach 2:
The phase-locked loop uses its feedback mechanism to detect and measure the actual delays introduced by peripheral circuits. The time-to-digital converter quantizes these delay values, which are then used to adjust timing parameters and compensate for the additional latency, maintaining synchronization accuracy despite the presence of multiple frequency-dividing and switching circuits
3Reliability
If system level calibration is performed to compensate for routing delays, then synchronization accuracy is improved, but measurement precision requirements increase
Solution Approach 1:
The system creates a digital copy of the actual delay values through the time-to-digital converter. Instead of requiring direct high-precision physical measurement, the analog delay is converted to a digital representation that can be stored and processed, reducing the demands on real-time measurement precision while maintaining overall synchronization accuracy through software-based compensation
Data Source
AI summary
A method determines a pin-to-pin delay between clock signals having integrally related frequencies. The method includes generating a delay code corresponding to a delay between a first signal edge of a first clock signal received by a first node of an integrated circuit and a second signal edge of a second clock signal received by a second node of the integrated circuit. The delay code is based on a first time code corresponding to the first signal edge, a second time code corresponding to the second signal edge, a first skew code, a second skew code, and a period of the first clock signal or the second clock signal. The first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is integrally related to the first frequency.