Clock Delay Compensation for Sub-Harmonic Oscillation in DC-DC Converters
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Solution Overview
Problem
Sub-harmonic oscillation occurs in peak-current-mode and valley-mode control switching converters due to instability caused by the difference between average inductor current and sampled inductor current, leading to alternating wide and narrow pulses at the switching node, which existing compensation methods fail to fully stabilize, especially at higher duty cycles.
Innovation Solution
A current-mode switching regulator with a high-side and low-side switch, synchronized by a system clock and a clock delay generation circuit that generates a delayed clock signal proportional or inversely proportional to the recent on-time of the switches, preventing sub-harmonic oscillation by adjusting the clock delay to counteract oscillatory effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a compensation signal is subtracted or added to prevent sub-harmonic oscillation, then stability is improved, but the control loop behavior deviates from ideal current converter operation and negative effects on the wider system occur
Solution Approach 1:
The patent introduces a current sampling mechanism that measures the actual inductor current and uses this sampled value as an intermediary to generate a compensated clock signal. This intermediary approach allows the system to achieve stability without directly manipulating the control loop in a way that would negatively affect wider system behavior, as the compensation is derived from actual current measurements rather than theoretical calculations.
Solution Approach 2:
The patent implements feedback by continuously sampling the inductor current and using this information to adjust the clock signal timing. The sampled current value feeds back into the control mechanism, allowing the system to dynamically compensate for sub-harmonic oscillation while maintaining proper current converter behavior. This feedback loop ensures stability without the negative side effects of traditional compensation methods.
2Stability of the object's composition
If traditional compensation methods are used to stabilize peak-current-mode or valley-mode control, then sub-harmonic oscillation is reduced, but the converter cannot remain fully stable across all duty cycles especially at higher duty cycles
Solution Approach 1:
The patent employs dynamic compensation by adjusting the clock signal timing based on the sampled inductor current value. Rather than using a fixed compensation amount, the system dynamically modifies the clock timing in response to actual operating conditions, allowing it to maintain stability across all duty cycles including higher duty cycles where traditional fixed compensation methods fail.
Solution Approach 2:
The patent changes the timing parameter of the clock signal based on the sampled current value. By varying the clock timing parameter dynamically according to actual inductor current measurements, the system adapts to different duty cycles and operating conditions, maintaining full stability where traditional methods with fixed parameters cannot.
Data Source
AI summary
The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.