Clock Delay Comparison for Low-Power Device Synchronization
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Solution Overview
Problem
Current methods for synchronizing devices require continuous monitoring by a processor, leading to power consumption issues and additional time for clock stabilization in phase locked loops.
Innovation Solution
A circuit and method for estimating time differences between signals using a delay unit, comparison unit, and difference estimator, which provides delayed versions of a signal for comparison with a reference signal to identify the closest match and estimate the time difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If continuous monitoring is used to synchronize devices, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The system uses periodic time difference measurements instead of continuous monitoring. The measurement unit periodically measures the time difference between clock signals from different devices, allowing synchronization to be maintained while reducing processor activity and power consumption compared to continuous monitoring approaches.
Solution Approach 2:
Each device autonomously measures its own time difference with other devices using its local measurement unit. This self-service approach eliminates the need for centralized continuous monitoring, allowing devices to independently maintain synchronization with reduced overall system power consumption.
2Measurement precision
If phase locked loop is used to update clock sources, then clock synchronization is improved, but additional stabilization time is required
Solution Approach 1:
The system replaces the traditional phase locked loop (PLL) mechanical/electrical stabilization process with a computational time difference measurement and adjustment approach. By directly measuring time differences and adjusting clock sources based on these measurements, the system achieves clock synchronization without requiring the extended stabilization time that PLL circuits need to settle.
Solution Approach 2:
The system performs preliminary time difference measurements before making clock source adjustments. By measuring the time difference ahead of time and calculating the required adjustment, the system prepares the synchronization correction in advance, avoiding the need for post-adjustment stabilization periods required by PLL-based approaches.
Data Source
AI summary
A time difference between an occurrence of a first event and an occurrence of a second event is estimated. A first time marker indicating the occurrence of the first event and a second time marker indicating the occurrence of the second event are received, wherein at least one event is one of playing a media frame or receiving a beacon. A plurality of delayed versions of the first time marker are provided, each being delayed by a different amount of delay to the other delayed versions. Each of the delayed versions of the first time marker are compared with the second time marker to identify which of the delayed versions of the first time marker is the closest temporally matching time marker to the second time marker. The time difference between the first and second time markers is estimated in dependence on the identified delayed version.