Clock Delay Control Circuit for Stable Frequency Multiplication
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Solution Overview
Problem
Conventional clock signal generation circuits face issues with stability and increased current consumption due to varying duty ratios and jitter in output clock signals, especially when generating clock signals with desired periods from input clock signals.
Innovation Solution
A clock signal generation circuit comprising a clock delay control signal generation unit to divide the clock signal, generate periodic signals for half periods, and output clock delay control signals, along with a doubler and quadrupler clock generation unit to delay and generate output clock signals with desired periods, reducing current consumption and stabilizing the output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a delay circuit and XOR gate are used to generate clock signals, then the frequency can be doubled, but the duty ratio changes significantly and jitter increases
Solution Approach 1:
The patent segments the clock signal generation into multiple independent paths: a main path that preserves the original clock signal characteristics, and a delayed path that generates phase-shifted signals. By dividing the function into separate segments (main clock path and delayed clock path), the duty ratio stability is maintained in the main path while frequency multiplication is achieved through controlled combination in the delayed path.
Solution Approach 2:
The patent introduces an intermediary delay circuit that generates delayed clock signals without directly affecting the main clock signal. This intermediary component (delay circuit with controllable delay amount) acts as a mediator between the original clock signal and the final output, allowing frequency multiplication while maintaining duty ratio stability through proper delay control.
2Reliability
If an oscillator and counter are used to generate clock signals, then phase and duty ratio stability is improved, but current consumption and circuit area increase
Solution Approach 1:
The patent uses periodic delay control signals generated from the original clock signal itself to control the delay amount. Instead of using a continuously operating oscillator, the system employs periodic sampling and delay control based on the clock signal's own periods, reducing continuous power consumption while maintaining phase stability through periodic synchronization.
Solution Approach 2:
The patent makes the delay circuit multi-functional by using it both for frequency multiplication and for maintaining phase stability. The same delay circuit that generates the delayed clock signals also provides the phase control necessary for stability, eliminating the need for separate oscillator and counter circuits and thereby reducing current consumption.
3Speed
If delay amount is increased to achieve frequency multiplication, then output frequency increases, but jitter of output clock signal increases
Solution Approach 1:
The patent employs dynamic delay control where the delay amount is adjusted based on the period of the input clock signal. The delay circuit dynamically adapts its delay amount to match the clock period, ensuring that frequency multiplication is achieved while maintaining consistent timing relationships and minimizing jitter through real-time adjustment.
Solution Approach 2:
The patent implements feedback mechanisms where the delay control signal generation unit uses the original clock signal to generate delay control signals that are fed back to the delay circuit. This feedback loop ensures that the delay amount is continuously adjusted to maintain optimal timing relationships, reducing jitter while achieving the desired frequency multiplication.
Data Source
AI summary
A clock signal generation circuit includes a clock delay control signal generation unit configured to divide a clock signal to generate a divided clock signal, generate a plurality of periodic signals which have different periods with each other during a half period of the divided clock signal, and output clock delay control signals from the plurality of periodic signals, and a doubler clock generation unit configured to delay the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generate an output clock signal by mixing phases of the clock signal and the delayed clock signal.