Clock Modulation Delay Hierarchy for Jitter-Tolerant Flip-Flops
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Solution Overview
Problem
Integrated circuits face challenges in scaling performance due to clock uncertainties such as clock jitter and skew, which are not reduced by technology scaling, limiting area and performance improvements in field programmable gate arrays (FPGAs).
Innovation Solution
A clock modulation circuitry with a delay hierarchy that includes first and second delay circuits and control circuitry to modulate clock signals, allowing flip-flops to function as soft-edge or time-borrowing flip-flops based on data path criticality, mitigating clock uncertainties and optimizing frequency and power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If technology scaling is used to increase circuit density, then area efficiency is improved, but clock uncertainty (jitter, skew) limits performance improvement
Solution Approach 1:
The clock signal is segmented into multiple phases using delay circuits, where each phase is delayed by a different amount. This segmentation allows different parts of the circuit to receive clock signals at optimally timed moments, thereby mitigating the effects of clock uncertainty while maintaining high circuit density.
Solution Approach 2:
The system dynamically selects among multiple delayed clock phases based on data path criticality. By making the clock phase selection dynamic and adaptive rather than fixed, the system can optimize performance for different operating conditions while maintaining area efficiency through technology scaling.
2Productivity
If clock delay circuits are added to mitigate clock uncertainty, then performance is improved, but area overhead increases
Solution Approach 1:
The delay hierarchy circuitry is merged with the existing clock distribution network and register structures. By integrating the delay functionality into the existing fabric rather than adding completely separate components, the system achieves performance improvement with minimal area overhead.
Solution Approach 2:
The delay hierarchy circuitry serves multiple functions: it provides clock phase adjustment, enables soft-edge flip-flop operation, supports time-borrowing modes, and adapts to different data path criticalities. This multi-functionality allows a single structure to deliver performance benefits across diverse circuit scenarios without proportionally increasing area.
3Ease of operation
If fixed clock edges are used in flip-flops, then timing analysis is simplified, but flexibility in handling critical data paths is reduced
Solution Approach 1:
The flip-flop edge characteristics are made dynamic rather than fixed. The delay hierarchy circuitry can configure the master and slave latches to operate in different modes (hard-edge, soft-edge, time-borrowing) based on the criticality of the data path, providing adaptability while maintaining timing analysis tractability through structured control.
Solution Approach 2:
The system changes the timing parameters of the flip-flop operation by adjusting the delay amounts in the delay circuits. By varying the delay parameters, the system can transform fixed-edge flip-flops into configurable structures that support soft-edge and time-borrowing operations, thereby increasing versatility without fundamentally changing the flip-flop architecture.
Data Source
AI summary
An integrated circuit (IC) includes a clock modulation circuitry including a delay hierarchy circuitry coupled to the register, the delay hierarchy circuitry configured to receive a clock (CLK) signal, provide a delayed master clock (CLKM) signal to a master latch of the register, and provide a delayed slave clock (CLKS) signal to a slave latch of the register.