Clock Propagation Path With Adjustable Delay for IC Timing Skew
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Solution Overview
Problem
Current integrated circuit design tools fail to accurately model and address clock skew, leading to hold time violations and reduced manufacturing yields, resulting in higher costs and delayed product launches due to race conditions and inefficient power consumption.
Innovation Solution
A circuit segment with a clock propagation path that delays clock signals by a clock delay interval related to the data propagation delay, using clock delay logic to generate and select delayed clock signals, allowing for adjustable delays during design, manufacturing, and post-fabrication to synchronize clocked devices and reduce clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are propagated through a distribution network to multiple storage elements, then all storage elements can be synchronized to a common clock, but clock skew causes timing differences that lead to hold time violations and race conditions
Solution Approach 1:
The patent divides the clock distribution network into multiple independent clock domains, each with its own clock signal and timing characteristics. Storage elements are grouped into different clock domains rather than being uniformly synchronized to a single clock signal, allowing each domain to operate with optimized timing parameters that prevent hold time violations while maintaining synchronization within that domain.
Solution Approach 2:
The patent introduces adjustable delay elements and programmable clock skew compensation mechanisms that allow the clock timing parameters to be dynamically adjusted after fabrication. This enables the system to compensate for manufacturing variations and physical property differences in real-time, ensuring hold time compliance despite variations in clock skew across different circuit implementations.
2Reliability
If the clock speed is reduced to prevent setup time violations, then timing constraints are met, but the maximum frequency and overall performance of the circuit is limited
Solution Approach 1:
By segmenting the circuit into multiple clock domains with different clock frequencies and phases, the patent allows different parts of the circuit to operate at different speeds. Critical paths can use higher frequency clocks while less critical paths use lower frequencies, preventing setup time violations in fast paths without limiting the overall performance of the circuit.
Solution Approach 2:
The patent employs programmable clock skew and adjustable timing parameters that allow the clock system to be optimized for different operating conditions. The clock parameters can be modified to match the actual propagation delays measured during testing, enabling the circuit to operate at higher frequencies while maintaining setup time compliance through precise timing control.
3Ease of manufacture
If design tools use simplified clock models, then the design process is simpler and faster, but they cannot accurately predict clock skew and hold time violations that occur after fabrication
Solution Approach 1:
The patent incorporates delay elements and skew compensation mechanisms into the design that are configured based on predicted clock skew values, even if those predictions are approximate. These preliminary configurations provide a first-order correction for clock skew, and the system includes adjustable parameters that can be fine-tuned after fabrication to achieve precise timing compliance.
Solution Approach 2:
The patent includes measurement and adjustment mechanisms that allow the actual clock skew to be measured after fabrication, and the clock timing parameters to be adjusted accordingly. This feedback loop enables the system to compensate for inaccuracies in the design-stage clock models by using actual measured values to configure the clock distribution network for optimal performance.
Data Source
AI summary
A method is provided for propagating clock signals in a circuit segment having a first clocked device, a second clocked device and a data path between the first clocked device and the second clocked device. The data path propagates data released by the first clocked device to the second clocked device and is associated with a data propagation delay. The method comprises providing a clock propagation path for propagating clock signals to the first clocked device and the second clocked device, wherein the clock signal propagated to the second clocked device is delayed from the clock signal propagated to the first clocked device by a clock delay interval, the clock delay interval being related to the data propagation delay of the data path. A circuit segment making use of the above method is also provided.