Clock Delay Compensation for Inter-Lane Skew in Die-to-Die Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased routing length differences in die-to-die interfaces lead to significant inter-lane skew during high-speed operations, which is not effectively addressed by existing designs, leading to inefficiencies and potential power consumption and chip area increases.
Innovation Solution
Implementing a circuitry with first and second sampling circuits that use clock signals with varying delays to align data transmission and reception across lanes with different connection line lengths, minimizing inter-lane skew without excessive power consumption or chip area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the die-to-die interface uses deep and narrow macros to increase bandwidth efficiency, then the die edge bandwidth density improves, but the routing length differences between lanes increase, causing increased inter-lane skew
Solution Approach 1:
The patent applies preliminary action by introducing delay elements to clock signals before they reach sampling circuits in longer lanes. This pre-compensation approach anticipates the skew problem caused by routing length differences and counteracts it in advance, ensuring that clock edges arrive at all lanes simultaneously despite varying path lengths.
Solution Approach 2:
The patent implements local quality by applying different delay amounts to clock signals based on their destination lane's routing length. Longer lanes receive clock signals with greater delay, while shorter lanes receive clock signals with lesser delay, creating a localized, lane-specific compensation strategy that equalizes arrival times across all lanes.
2Manufacturing precision
If traditional skew compensation methods are used, then inter-lane skew may be reduced, but power consumption and chip area increase significantly
Solution Approach 1:
The patent applies parameter changes by adjusting the delay amount of clock signals as a controllable parameter. By varying the delay parameter based on lane-specific routing lengths rather than using fixed, excessive compensation, the system achieves effective skew reduction while minimizing unnecessary power consumption and chip area usage.
3Manufacturing precision
If traditional skew compensation methods are used, then inter-lane skew may be reduced, but chip area expands excessively
Solution Approach 1:
The patent uses parameter changes to optimize the delay compensation approach, adjusting delay amounts precisely to match routing length differences. This prevents over-compensation and the associated chip area expansion that would result from traditional methods using uniform, excessive delay elements across all lanes.
Data Source
AI summary
The present invention provides a circuitry including a first sampling circuit and a second sampling circuit. The first sampling circuit is configured to use a first clock signal to sample first data to generate sampled first data to a plurality of first lanes of a transmitter via a plurality of first connection lines. The second sampling circuit is configured to use a second clock signal to sample second data to generate sampled second data to a plurality of second lanes of the transmitter via a plurality of second connection lines. Lengths of the plurality of second connection lines are longer than lengths of the plurality of first connection lines, and delay amount of the second clock signal is less than delay amount of the first clock signal.