Interpolated Clock Delay Generation for Sub-Gate Resolution
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Solution Overview
Problem
Conventional delay-locked loops have a minimum resolution greater than or equal to the propagation delay of one delay component, limiting their application in specific fields due to inability to provide smaller resolution.
Innovation Solution
A clock generating device comprising a first timing delay module, a multiplex module, and a second timing delay module, where the multiplex module selects two delayed clock signals from a plurality generated by the first timing delay module, and the second timing delay module generates an output clock signal, achieving high linearity by employing timing interpolation units and multiplexers to control the delay components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional delay-locked loop uses a series of delay components to delay clock signals, then the circuit structure is simple and easy to manufacture, but the minimum resolution is greater than or equal to the propagation delay of one delay component, limiting the ability to provide smaller resolution
Solution Approach 1:
The patent divides the delay adjustment into two stages: a coarse delay stage using a delay-locked loop with multiple delay components, and a fine delay stage using an interpolation circuit that combines adjacent delayed clock signals. This segmentation allows the system to achieve sub-component resolution by interpolating between discrete delay steps, thereby improving minimum resolution without proportionally increasing overall circuit complexity
Solution Approach 2:
The patent introduces a multiplexer as an intermediary component that selects and combines adjacent delayed clock signals from the delay-locked loop. By using the multiplexer to interpolate between discrete delay stages, the system achieves finer resolution control without directly modifying the core delay components, thus improving precision while managing complexity
2Manufacturing precision
If the delay-locked loop provides discrete delay steps based on propagation delay of delay components, then the device complexity is low, but the linearity of delay control is poor due to inability to provide continuous delay adjustment
Solution Approach 1:
The patent implements dynamic delay adjustment by enabling continuous variation of the output clock signal delay through the interpolation circuit. The system dynamically combines adjacent delayed clock signals in varying proportions based on control signals, transforming the static discrete delay steps into a dynamic continuous delay range, thereby improving linearity while accepting increased device complexity
Solution Approach 2:
The patent changes the delay parameter from discrete fixed values to continuous variable values by introducing the interpolation mechanism. The output delay becomes a variable parameter that can take any value within the range defined by adjacent delay components, achieving superior linearity through parameter continuity rather than fixed discrete steps
Data Source
AI summary
A clock generating device includes a first timing delay module, a multiplexer, and a second timing delay module. The multiplexer is electrically connected to the first timing delay module. The second timing delay module is electrically connected to the multiplexer. The first timing delay module generates a plurality of delayed clock signals based on a reference clock signal. The multiplexer outputs a first delayed clock signal and a second delayed clock signal, among the plurality of delayed clock signals, based on a clock generating signal. The second timing delay module generates an output clock signal based on the clock generating signal, the first delayed clock signal and the second delayed clock signal.