Clock Delay Path With Inverting Repeaters for Stable Duty Ratio
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining a consistent duty ratio of clock signals due to variations in process, voltage, and temperature (PVT), which affect the performance of internal clock signals and data strobe signals.
Innovation Solution
The implementation of a clock signal delay path unit with long metal lines and repeaters that include inverting circuits to correct duty ratio changes by inverting the phase of clock signals, ensuring a consistent duty ratio output despite PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If long metal lines are used to transmit clock signals over distance, then signal transmission capability is improved, but signal attenuation occurs
Solution Approach 1:
Repeaters are introduced as intermediary components along the long metal lines to receive attenuated clock signals, restore their strength, and retransmit them. This mediator approach allows the signal to maintain adequate amplitude over extended distances without direct degradation from the source to the destination.
Solution Approach 2:
The long transmission path is divided into multiple segments by inserting repeaters at intermediate points. Each segment becomes a manageable transmission unit where signal attenuation is controlled and compensated, rather than dealing with the entire long distance as a single problematic path.
2Adaptability or versatility
If process, voltage, and temperature variations occur, then manufacturing adaptability is improved, but duty ratio consistency deteriorates
Solution Approach 1:
The delay-locked loop continuously monitors the phase relationship between the external clock signal and the internal delayed clock signal, using feedback control to adjust delay elements and maintain accurate duty ratio despite PVT variations. The feedback mechanism detects deviations and compensates for them in real-time.
Solution Approach 2:
The delay-locked loop dynamically adjusts delay parameters of clock signal paths to compensate for PVT variations. By changing the delay characteristics of buffer circuits and transmission lines, the system maintains consistent duty ratio across varying process conditions, voltages, and temperatures.
3Reliability
If delay locked loop is used to generate delayed clock signal, then clock signal synchronization is improved, but additional circuit complexity is introduced
Solution Approach 1:
The delay-locked loop is designed to perform multiple functions simultaneously: generating delayed clock signals, maintaining duty ratio consistency, providing phase synchronization, and compensating for PVT variations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting additional complexity.
4Stability of the object's composition
If repeaters with inverting circuits are used to correct duty ratio, then duty ratio consistency is improved, but device complexity increases
Solution Approach 1:
The inverting circuit functionality is merged with the repeater structure rather than being implemented as a separate component. This integration allows duty ratio correction and signal regeneration to occur in a single unified circuit block, reducing overall device complexity while maintaining the necessary functionality for consistent duty ratio output.
Data Source
AI summary
A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.