Bias-Controlled Clock Path Delay for Power Supply Jitter Compensation
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Solution Overview
Problem
Memory devices experience clock jitter due to variations in power supply voltage and current, which affect the synchronization of operations and can lead to time variations in clock signals and outputs, even within specified operating parameters.
Innovation Solution
The implementation of jitter compensation circuits that modulate delay with respect to bias current or voltage to counteract the sensitivity of clock path components to power supply variations, using bias-controlled delay elements and phase mixing of clock paths to stabilize clock signals across different power levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock path components are used to generate and distribute clock signals, then clock synchronization is achieved, but power supply variations cause time variation (jitter) in the clock signal
Solution Approach 1:
The patent implements feedback mechanisms where delay measurement circuits continuously monitor the delay of clock signals through feedback paths. The measured delay information is used to adjust bias currents in delay elements, creating a closed-loop system that compensates for power supply variations and maintains stable clock timing.
Solution Approach 2:
The patent changes the bias current parameter of delay elements dynamically based on measured delay conditions. By adjusting the bias current, the delay characteristics of clock path components are modified to compensate for variations caused by power supply changes, thereby stabilizing the clock signal timing.
2Reliability
If bias current is increased to reduce delay variation, then clock signal stability improves, but power consumption increases
Solution Approach 1:
The patent employs dynamic adjustment of bias currents rather than fixed high current levels. The bias current is modulated based on real-time delay measurements, allowing the system to maintain clock stability only when necessary and reducing power consumption during normal operating conditions.
Solution Approach 2:
The system uses its own delay measurements to automatically adjust its bias currents without external intervention. The clock path components self-regulate their operating points based on feedback from delay measurement circuits, eliminating the need for continuous high power consumption to maintain stability.
3Measurement precision
If delay elements are added to compensate for jitter, then clock timing accuracy improves, but device complexity increases
Solution Approach 1:
The patent designs delay elements that serve multiple functions: they are part of the normal clock distribution path and simultaneously serve as adjustable timing compensation elements. The same delay elements used for clock signal distribution are also used for jitter compensation through bias current adjustment, eliminating the need for separate compensation circuits.
Solution Approach 2:
The patent merges the delay measurement function with the clock distribution function by creating feedback paths that reuse existing clock path infrastructure. The bias-controlled delay elements are integrated into the normal clock distribution network, combining timing adjustment capabilities with signal distribution without adding completely separate circuitry.
Data Source
AI summary
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.