Current-Starved Clock Delay Circuit for Low-Power IoT Readout
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Solution Overview
Problem
Existing sensor readout circuitry for IoT applications faces challenges in minimizing power dissipation while maintaining low power consumption and efficient clock generation, as prior art clock generation circuitry is susceptible to unwanted power dissipation.
Innovation Solution
A clock delay circuit is designed with a current mirror and Schmitt trigger configuration that generates a delayed clock signal by scaling reference currents and controlling capacitor charging, reducing power dissipation through current starving of Schmitt triggers and inverters during charging periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock generation circuitry is used in sensor readout circuitry, then the circuit can generate necessary clock signals for sensor polling and data acquisition, but the circuit suffers from unwanted power dissipation that reduces battery life
Solution Approach 1:
The clock generation circuit is designed to operate in periodic intervals rather than continuously. The circuit remains in a low-power state during idle periods and activates only when sensor polling or data acquisition is required. This periodic operation pattern significantly reduces average power dissipation while maintaining the ability to generate necessary clock signals when needed.
Solution Approach 2:
The circuit employs dynamic power management by adjusting its operational state based on system requirements. Delay elements are configured to dynamically control the timing and duration of clock signal generation, allowing the circuit to transition between active and low-power states. This dynamic behavior optimizes power dissipation by ensuring the circuit operates at full power only when necessary for sensor operations.
2Loss of energy
If the circuit remains completely off when not polling sensors to minimize power dissipation, then power consumption is reduced, but the circuit must wake up quickly when sensor data acquisition is required
Solution Approach 1:
The circuit performs preliminary configuration of delay elements and clock generation parameters during idle low-power states, preparing for rapid activation. Critical timing parameters are pre-calculated and stored, allowing the circuit to quickly transition to active state when sensor polling is required without requiring extensive setup time upon waking.
Solution Approach 2:
The circuit incorporates feedback mechanisms that monitor system state and sensor requirements, triggering wake-up events at optimal moments. The feedback system ensures the circuit activates precisely when sensor data acquisition is needed, minimizing unnecessary wake-up cycles and associated power consumption while ensuring rapid response when required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively limits short currents and reduces power dissipation by current starving components during charging, enabling efficient clock generation with lower power consumption, thus extending battery life in IoT sensor applications.
Implementation Method 1
a capacitor configured to charge or discharge based on the input clock signal and an output clock signal, the capacitor having a capacitance (C)
Implementation Method 2
a current mirror configured to generate one or more starved currents based on the reference current and having a current scaling factor and configured to provide a scaled version of the reference current at the top node, scaled by a current scaling factor (N TOP)
Implementation Method 3
a Schmitt trigger configured to generate a Schmitt trigger output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a charging period of time (T CHARGE ) correlated with T DEL , in response to a high signal input from the input clock signal, via the switching module, the high signal based on an upper threshold voltage (V ST, High ) of the Schmitt Trigger
Data Source
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AI summary
A clock delay circuit is configured to generate a delayed clock signal based on an input clock signal, the delayed clock signal delayed by a delay time (TDEL). The circuit includes a current mirror configured to generate starved currents based on the reference current, a plurality of inverters, and a Schmitt trigger configured to generate an output signal in response to the input clock signal, wherein the Schmitt trigger output signal increases from a low signal to a high signal over a period (TCHARGE) correlated with TDEL. Some inverters and the Schmitt trigger are configured to be current starved when the input clock signal is high and are configured to be shorted to ground and the reference current when the input clock signal is low. TDEL is based on TCHARGE and TCHARGE is based on C, NTOP, VST, High, and a supply voltage.