TDC-Based Clock Delay Using Memory for Wide-Range PLL Alignment
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in achieving both high resolution and large delay ranges, as existing analog delay methods provide high resolution but limited delay ranges, while digital delays offer large ranges but lack high resolution.
Innovation Solution
The use of time-to-digital converters (TDCs) coupled with memory to convert clock signal edges into digital values, which are then stored and dequeued after a predetermined delay, allowing for high-resolution and large-range signal delays within a phase-locked loop system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog delays are used to delay input signals, then high resolution is achieved, but large delay ranges cannot be accommodated
Solution Approach 1:
The delay function is segmented into two independent components: an analog delay chain for high-resolution fine-tuning and a digital counter for large-range coarse adjustment. This segmentation allows each component to specialize in one aspect of the delay requirement, combining their capabilities to achieve both high resolution and large delay range simultaneously.
Solution Approach 2:
The patent merges the analog delay chain and digital counter into a unified delay system. The analog delay provides fine resolution control while the digital counter extends the overall delay range, creating a hybrid delay mechanism that achieves both high resolution and large delay range that neither component could achieve alone.
2Adaptability or versatility
If digital delays are used to delay input signals, then large delay ranges are provided, but high resolution is lost
Solution Approach 1:
The delay function is segmented into two independent parts: a digital counter for large-range coarse delay and an analog delay chain for high-resolution fine-tuning. This segmentation allows the digital component to handle the delay range requirement while the analog component restores the resolution that would otherwise be lost.
Solution Approach 2:
The patent combines the digital counter and analog delay chain into a hybrid delay system where the digital counter provides the foundation for large delay ranges and the analog delay chain adds the necessary fine resolution, achieving both large delay range and high resolution simultaneously.
3Reliability
If input signals are buffered while quality is analyzed, then lower quality inputs are prevented from adversely affecting PLL output, but additional delay complexity is introduced
Solution Approach 1:
The hybrid delay system serves multiple functions: it buffers input signals for quality analysis, provides programmable delay for signal alignment, and enables seamless switching between reference clock sources. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall system complexity while maintaining reliability.
Data Source
AI summary
A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.