Clock Path Delay Control for Fast Metastable Frequency Reduction
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Solution Overview
Problem
Current electronic devices face performance limitations due to power supply noise, which is exacerbated by high current density and finite power supply impedance, leading to the need for rapid and robust reduction of clock frequency to prevent timing failures, but existing methods are hindered by metastability issues with digital feedback signals.
Innovation Solution
An electronic device with a clock path and an analogue element that varies the switching delay of the clock propagating element based on the analogue level of a digitally sampled signal, allowing for continuous adjustment of clock frequency without causing malformed clock signals, even when the signal is metastable, enabling fast frequency reduction within one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronizer circuit is used to eliminate metastability in the control signal, then reliability is improved, but the response time deteriorates due to multiple cycles of delay
Solution Approach 1:
The invention extracts and removes the synchronizer circuit from the control path, taking out the source of delay. By eliminating the synchronizer, the control signal passes directly to the clock frequency control without undergoing multiple cycles of delay, thus resolving the contradiction between reliability improvement and time loss.
Solution Approach 2:
Instead of using a synchronizer to handle metastability (conventional approach), the invention inverts the approach by directly using the potentially metastable control signal to modulate the clock frequency. The analogue element processes the control signal without synchronization, achieving frequency reduction without the time penalty of synchronizer delays.
2Speed
If the loop bandwidth of the PLL is increased to enable faster clock frequency changes, then speed is improved, but jitter (phase noise) increases which makes it impractical
Solution Approach 1:
The invention segments the clock frequency control into two independent parts: (1) the PLL maintains its original low bandwidth for stable jitter performance, and (2) a separate analogue control element directly modulates the clock propagating element's delay. This segmentation allows fast frequency changes without compromising jitter control, as each component operates in its optimal range.
Solution Approach 2:
The invention introduces an intermediary analogue element (such as a variable delay element or capacitance element) between the control signal and the clock propagating element. This intermediary directly adjusts the clock delay without requiring PLL bandwidth changes, enabling fast frequency reduction while maintaining the PLL's low-jitter characteristics.
3Reliability
If supply voltage margins are increased to ensure reliable digital circuit timing, then reliability is improved, but power consumption increases
Solution Approach 1:
The invention makes the clock frequency dynamic and adaptive rather than fixed. By continuously monitoring timing margins and automatically reducing clock frequency when margins become insufficient, the system maintains timing reliability without needing permanently high supply voltage margins, thus reducing overall power consumption while preserving reliability.
Solution Approach 2:
The invention changes the operating parameters of the clock circuit by dynamically adjusting the clock frequency based on real-time timing margin conditions. When timing margins deteriorate, the clock frequency is reduced, which allows reliable operation at lower supply voltages, thereby reducing power consumption while maintaining timing reliability.
Data Source
AI summary
An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.