Clock Delay Adjustment Circuit Using Miller-Effect Capacitance
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Solution Overview
Problem
Four-phase clocking systems in memory devices face challenges due to phase-to-phase offset issues, where some phases can become out of sync, leading to timing problems that are difficult to mitigate.
Innovation Solution
The use of amplifiers acting as variable capacitors, controlled by adjusting currents through them, to manage delays between buffer stages, effectively mitigating phase-to-phase delay issues by altering the apparent capacitance seen by signal lines through the Miller-effect, and employing differential amplifiers on specific phases to synchronize clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four-phase clocking is used to increase operating speed, then productivity is improved, but phase-to-phase offset issues cause timing errors that worsen reliability
Solution Approach 1:
The patent adjusts the gain of amplifiers as a variable parameter to control the delay of clock signals. By changing the gain parameter of amplifiers coupled to different phases, the system dynamically compensates for phase-to-phase delays and synchronizes the clock phases, resolving the timing accuracy issues while maintaining high operating speeds
2Measurement precision
If amplifiers are used to control signal delays, then timing precision is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent employs amplifiers that serve dual functions: they provide necessary signal buffering and simultaneously act as variable capacitors through the Miller effect to control signal delays. This multi-functionality reduces the need for separate delay control circuits, thereby managing device complexity while achieving precise timing control
3Measurement precision
If amplifier gain is adjusted to synchronize phases, then timing accuracy is improved, but energy consumption increases due to active control requirements
Solution Approach 1:
The patent utilizes the inherent Miller effect of the amplifiers to create variable capacitance that automatically adjusts the signal delays. This self-service mechanism leverages the natural electrical behavior of the amplifier circuits to achieve phase synchronization without requiring additional active control elements, thereby reducing overall energy consumption while maintaining timing accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the clock signals by adjusting the gain of amplifiers, ensuring that phases remain synchronized, thereby reducing timing errors and improving the reliability of memory operations.
Implementation Method 1
The use of amplifiers acting as variable capacitors, controlled by adjusting currents through them, to manage delays between buffer stages, effectively mitigating phase-to-phase delay issues by altering the apparent capacitance seen by signal lines through the Miller-effect
Data Source
AI summary
Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.