Memory Controller Clock Delay Tuning for Unmatched NAND Data Paths
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Solution Overview
Problem
In non-volatile memory systems, the alignment of data and clock signals at the memory die's receiver circuit is often mismatched in an unmatched data input path architecture, leading to improper latching and inefficiencies.
Innovation Solution
A memory controller compensates for this mismatch by determining and introducing individual relative delay values to the clock signal path based on the relative power consumption of each memory die, ensuring proper alignment of data and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an unmatched data input path architecture is used to reduce device complexity and power consumption, then device complexity and power consumption are reduced, but signal alignment between data and clock signals deteriorates
Solution Approach 1:
The patent applies preliminary action by measuring and determining relative delay values for each memory die before normal data operations. The memory controller pre-characterizes each die's signal path delays and stores these values for use during runtime, allowing the system to compensate for path mismatches without requiring complex hardware matching circuits.
Solution Approach 2:
The patent changes the timing parameter of the clock signal by introducing variable delays based on measured relative delay values. The memory controller adjusts the clock signal phase individually for each memory die using the pre-determined delay values, thereby compensating for unmatched data path lengths and achieving proper signal alignment.
2Use of energy by stationary object
If an unmatched data input path architecture is used to reduce power consumption, then power consumption is reduced, but signal alignment between data and clock signals deteriorates
Solution Approach 1:
The system performs preliminary measurement of relative delay values for each memory die during initialization or characterization phase. These pre-determined values are stored and reused during normal operations, avoiding the need for continuous complex timing adjustments while maintaining proper signal alignment and reducing overall power consumption.
Solution Approach 2:
The patent creates a virtual model of each memory die's timing characteristics by measuring and storing relative delay values. This timing profile copy is then used to predict and compensate for signal alignment issues without requiring complex real-time measurement circuits, thereby reducing power consumption while maintaining alignment precision.
3Manufacturing precision
If individual relative delay values are introduced to each memory die to improve signal alignment, then signal alignment is improved, but device complexity increases
Solution Approach 1:
Each memory die effectively serves itself by having its unique relative delay value stored and applied by the controller. The measurement and characterization process is automated, and the system uses the pre-determined delay values to automatically compensate for each die's specific timing characteristics without requiring manual intervention or complex real-time adjustment mechanisms.
Solution Approach 2:
The controller manages complexity by changing only the timing parameter of the clock signal based on pre-determined relative delay values for each die. This approach avoids the need for complex physical reconfiguration or additional hardware circuits, as the compensation is achieved through simple parameter adjustment of existing signals.
4Productivity
If individual relative delay values are introduced to each memory die to improve data latching efficiency, then data latching efficiency is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary characterization of each memory die's timing characteristics and stores relative delay values before normal operations begin. This pre-work enables efficient data latching during runtime without requiring complex real-time measurement and adjustment mechanisms, thereby improving productivity while managing controller complexity.
Data Source
AI summary
In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.